Design Validation Techniques: A Tutorial

Abstract

The increasing complexity of VLSI systems has resulted in the verification problem for such designs becoming more and more difficult. Indeed, verification has become the bottleneck in the IC design process today, with validation teams often being comparable in size to design teams. This tutorial covers the whole gamut of state-of-the-art verification techniques and also introduces some new ideas that can be used to verify designs in a fraction of the time taken by traditional tools. These ideas have been incorporated in a number of university and commercial CAD tools; it is expected that they will become an integral part of the design flow of the future.

The tutorial will provide detailed descriptions of the following topics: (1) computational models for designs, (2) state-of-the-art simulation techniques, (3) emulation methodology, (4) BDD-based methods for checking the equivalence of gate-level designs, (3) formal verification of properties using model checking, and (4) efficient algorithms for timing verification. Theory will be reinforced by practice through the use of software demonstrations. A special emphasis will be placed on techniques which can handle large scale designs and are already being used (or are expected to be used in the very near future) by many design houses in their design flow.

For comments contact anarayan@ic.eecs.berkeley.edu