Huey-Yih Wang

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Huey-Yih is a Ph.D. candidate in the EECS Department of University of California at Berkeley . He is in the Computer-Aided Design (CAD) group. His research advisor is Prof. Robert K. Brayton .

• Home phone: (510) 548-9620
• Office phone: (510) 643-7039
• Office FAX: (510) 643-5052
• Email address: hywang@eecs.berkeley.edu
• Mail address: 207-212 Cory Hall, University of California, Berkeley, CA 94720-1772

Personal Information

• Birthplace: Taipei, Taiwan, R.O.C .
• B.Sc. from the Department of Electrical Engineering at the National Taiwan University , Taiwan, R.O.C.

Research Interests

• Hierarchical Sequential Synthesis --- Logic Optimization of FSM Networks
• Sequential ATPG
• Technology Mapping
• Formal Verification

Publications

• H. Savoj, H-Y. Wang, and Robert K. Brayton,
  "Improved Scripts in MIS-II for Logic Minimization of Combinational Circuits."
  In Proceedings of the International Workshop on Logic Synthesis, May 1991.
• R. K. Brayton, M. Chiodo, R. Hojati, T. Kam, K. Kodandapani, R. P. Kurshan, S. Malik, A. Sangiovanni-Vincentelli, E. M. Sentovich, T. Shiple, and H.-Y. Wang,
  "BLIF-MV: An Interchange Format for Design Verification and Synthesis."
  Memorandum No. UCB/ERL M91/97, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720.
• H.-Y. Wang and R. K. Brayton,
  "Computation of Sequential Input Don't Care Sequences in FSM Networks of Arbitrary Topologies."
  In Proceedings of the International Workshop on Logic Synthesis, May 1993.
• H.-Y. Wang and Robert K. Brayton,
  "Permissible Observability Relations in Interacting Finite State Machines."
  In Proceedings of the International Workshop on Logic Synthesis, May 1993.
• T. Shiple, A. Aziz, F. Balarin, S.-T. Cheng, R. Hojati, T. Kam, S. C. Krishnan, V. Singhal, H.-Y. Wang, R. K. Brayton, and A. Sangiovanni-Vincentelli,
  "Formal Design Verification of Digital Systems."
  In Proceedings of the SRC TECHCON, pp. 294-296, Altanta, Georgia, September 1993.
• H.-Y. Wang and R. K. Brayton,
  "Input Don't Care Sequences in FSM Networks."
  In Proceedings of the International Conference on Computer-Aided Design, pp. 321-328, November 1993. Also in Memorandum No. UCB/ERL M93/64, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, 1993.
• H.-Y. Wang and R. K. Brayton,
  "Permissible Observability Relations in FSM Networks."
  In Proceedings of the Design Automation Conference, pp. 677-683, June 1994. Also in Memorandum No. UCB/ERL M94/15, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, 1994.
• A. Aziz, F. Balarin, S.-T. Cheng, R. Hojati, T. Kam, S. C. Krishnan, R. Ranjan, T. Shiple, V. Singhal, S. Tasiran, H.-Y. Wang, R. K. Brayton, and A. Sangiovanni-Vincentelli,
  "HSIS : A BDD-Based Environment for Formal Verification."
  In Proceedings of the Design Automation Conference, pp. 454-459, June 1994.
• H.-Y. Wang and R. K. Brayton,
  "Logic Optimization of FSM Networks Using Input Don't Care Sequences."
  Memorandum No. UCB/ERL M95/42, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720.
• H.-Y. Wang and R. K. Brayton,
  "Multi-level Logic Optimization of FSM Networks."
  To appear in Proceedings of the International Conference on Computer-Aided Design, November 1995. Also in Memorandum No. UCB/ERL 95/66 of Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720.

Hobbies

• Bowling
• Reading
• Singing

Favorite Pictures

I recently went to Disneyland and had a blast!