Errata for Function/Architecture
Optimization and Co-design of Embedded Systems
o
P. 4, 2nd paragraph: "...speedmetrics of execution of the
software".
o
P. 14, 3rd bullet: "...we should to allow the designer".
o
P. 15, 2nd paragraph: "Figure 2.2 shows
... Accuracy vs. Throughputthroughput
trade-off ...".
o
P. 15, 3rd paragraph: "...so the method
also models the interfaces between among...".
o P. 16, in Figure 2.2 "My approach" should be "Our approach".
o
P. 18, “We have developed on a novel top-down…”.
o P. 20, 2nd paragraph: “… re-targeted if new target platforms become available”.
o P. 21, “MACs”.
o
P. 24, “…analysis techniquesanalysis techniques…”
o P. 39, 2nd paragraph: “… the FFG onto various computation models, and the CFSM model is only one of those.”.
o P. 39, 3rd paragraph: “…—based on the user’s functional… EFSM—onto the (initially unscheduled) FFG to obtain…”.
o P. 55, 3rd paragraph “We are now ready …”
o P. 56, Property 4.2.1: “Given ….. ["x, …] if and only if ["x, …]”
o P. 67, 1st paragraph, “…, and store the…”
o P. 67, 1st paragraph, “…where a variable is used, for example:”
o P. 69, top, “…this (unreachable) node and not …”
o
P. 76, paragraph right after proof of Theorem 4.4.2,
“…. for the external iteration of the FFG optimization AlgorithmOptimization.”
o P. 77, last paragraph, “….so the optimization is quite desirable…”
o
P. 87, Section 5.2, “In this Chapter, we consider the
AFFG which has a set of attributesattributes
associated with…”
o
P. 91, Section 5.3.4, “(b) Reverse Sweep: … that we am are mainly ….”
o P. 98, Table 5.1, (small, rainy) should have an NPT entry of (1,0) for (Indoors, Outdoors)
o P. 105, Definition 5.5.1, 1st bullet: “Each node in G must belong to a state i.e. …”
o
P. 108, 1st paragraph, “In words, Algorithm
5.5.2 shown …. Untile we hit the
next state boundary. If we encounter …”
o P. 109, Register Allocation Algorithm, the external loop “foreach node nÎ G do … end foreach” should be removed.
o P. 112, 2nd paragraph, “Again…; for our purposes here we will always use of Algorithm 5.5.3 for maximum speedup.”
o
P. 113, Section 5.6, “System level design has a fractal
nature;….. Function/architecture co-designan
can be performed at the ….”
o P. 116, Figure 5.11 is missing a labeling that identifies an example recommendation from the function onto the architecture instruction/resource selection as following:
[t1 = 3*b
t2 = t1 + a]
MAC(b, 3, a); // multiply b by 3 and add to a
emit x(t2)
o P 117, 1st paragraph, “Similarly … can be relaxed to make expressions that depend on input valuations available, if possible, based on the CFSM sampling criteria.
o
P. 117, “The goal in wire removal is to attempting to reduce …”
o
P. 118, “… a node in the Boolean network, and don’t
cares are used to reflect that the output node is not controllabler or that the input change effect is
not observable at this output.”
o P. 118, 2nd paragraph, “In the SoC IP-assembly domain, because of sheer complexity logic synthesis cannot hope …”
o
P. 137, Paragraph after Example 6.5.2, “We are
currently experimenting with the ITE substitution heuristicheuristic in conjunction …”
o P. 172, Section 7.10.5, “We are exploring opportunities for statically modeling optimization …”
o P. 173, Last paragraph, “Another simple improvement …. to consist of a set of values that capture …”
o P. 177, Footnote 1, “As promised in the This Work’s Contribution Section of Chapter 1”
o P. 179, 2nd paragraph, “A DFA framework would be …. optimization, in our opinion, because of …”
o P. 180, 1st paragraph, “Our goal here is to improve this initial functional decomposition.”
o P. 180, 1st paragraph, “The main idea behind our procedure is that the larger the size of the task …”
o P. 187, 2nd paragraph, “Our software architecture design follows Object Oriented Programming …”
o P. 213, 2nd paragraph, “... an area which has been active for the past two decades …”
o
P. 214, 2nd paragraph, “In this work, we
have assumed an initial functional decompositionfunctional possibly …”
o
P. 214, “ … ‘wire up’ …”
Maintained by Bassam Tabbara (tbassam@eecs.berkeley.edu)