Publications

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Conference publications

Generalized Cofactoring for Logic Function Evaluation
Yunjian Jiang, Slobodan Matic, and Robert Brayton
Design Automation Conference (DAC), Anaheim, June 2003.
Extended version
State-Based Power Analysis for Systems-on-Chip
Reinaldo Bergamaschi and Yunjian Jiang
Design Automation Conference (DAC), Anaheim, June 2003.
Don't Cares in Logic Minimization of Extended Finite State Machines
Yunjian Jiang and Robert Brayton
Asia South Pacific Design Automation Conference (ASP-DAC), Kitakyushu, Jan 2003.
Software Synthesis from Synchronous Specifications Using Logic Simulation Techniques
Yunjian Jiang and Robert K. Brayton
Design Automation Conference (DAC), New Orleans, June 2002.
HW/SW Partitioning and Code Generation of Embedded Control Applications on a Reconfigurable Architecture Platform
Massimo Baleani, Frank Gennari, Yunjian Jiang, Yatish Patel, R. K. Brayton, Alberto Sangiovanni-Vincentelli
International Symposium of Hardware/Software Codesign (CODES), Estes Park, Colorado, May 2002.
Optimization of Multi-Valued Multi-Level Networks
M. Gao, J-H. Jiang, Y. Jiang, Y. Li, A. Mishchenko, S. Sinha, T. Villa and R. Brayton
International Symposium on Multiple-Valued Logic (ISMVL), 2002
Logic optimization and code generation for embedded control applications
Yunjian Jiang and Robert K. Brayton
International Symposium of Hardware/Software Codesign (CODES), Copenhagen Denmark, Apr. 2001.
Don't cares and multi-valued logic network minimization
Yunjian Jiang and Robert K. Brayton
International Conference on Computer-Aided Design (ICCAD), Santa Clara, Nov. 2000.

Workshop Presentations

An Information Theoretic Approach to Logic Evaluation
Yunjian Jiang and Robert Brayton
International Workshop on Logic Synthesis (IWLS), Anaheim, June 2003
Don't Care Computation in Minimizing Extended Finite State Machines with Presburger Arithmetic
Yunjian Jiang and Robert Brayton
International Workshop on Logic Synthesis (IWLS), New Orleans, June 2002
MVSIS
Minxi Gao, Jie-Hong Jiang, Yunjian Jiang, Yinghua Li, Subarna Sinha and Robert Brayton
International Workshop on Logic Synthesis (IWLS), Tahoe City, June 2001
Minimization of Multiple-Valued Functions in Post Algebra
Elena Dubrova, Yunjian Jiang and Robert Brayton
International Workshop on Logic Synthesis (IWLS), Tahoe City, June 2001
An implicit method for multi-valued network encoding
Jie-Hong Jiang, Yunjian Jiang and Robert K. Brayton
International Workshop on Logic Synthesis (IWLS), Tahoe City, June 2001
An Optimizing Software Compiler Based on Multi-Valued Logic Optimization
Yunjian Jiang, Minxi Gao, Subarna Sinha, and Robert K. Brayton
TechCON, Semiconductor Research Corporation, Pheonix, Sep. 2000.
Don't Care Wires in Logical/Physical Design
Philip Chong, Yunjian Jiang, Sunil Khatri, Fan Mo, Subarna Sinha and Robert Brayton
International Workshop on Logic Synthesis (IWLS), Dana Point, May 2000.
Don't Cares and Multi-valued Logic Minimization
Yunjian Jiang and Robert K. Brayton
International Workshop on Logic Synthesis (IWLS), Dana Point, May 2000.

Technical Report

Multi-Valued logic network minimization and it's applications
Yunjian Jiang
Master's thesis, EECS Dept., Technical Report UCB/ERL M00/26, Electronics Research Laboratory, University of California, Berkeley, May 2000.
Don't Care Wires in Logical/Physical Design
Philip Chong, Yunjian Jiang, Sunil Khatri, Subarna Sinha and Robert Brayton
Technical Report UCB/ERL M99/52, Electronics Research Laboratory, University of California, Berkeley, Nov. 1999
A Multi-Layer Routing Methodology Using a Boolean Satisfiability-based Router
Yunjian Jiang, Sunil Khatri, Alberto Sangiovanni-Vincentelli and Robert Brayton,
Technical Report UCB/ERL M99/16, Electronics Research Laboratory, University of California, Berkeley, Mar. 1999
Macro Instruction Synthesis for Embedded RISC Processors
Yunjian Jiang and Pinhong Chen
project report, May. 2000.
Protocol Converter Synthesis: An application of control synthesis
Yunjian Jiang and Yujia Jin
project report, Dec. 1999.