Research Interests

Hardware-software codesign of embedded systems; Design methodologies, behavioral modeling and synthesis tools for communication protocols; Combinational and sequential logic optimizations; Circuit simulation; Design methodologies for emerging devices, including multi-valued current-mode and optical switching devices; Application of information theory in Boolean reasoning.

Education

University of California, Berkeley
Berkeley California

Ph. D. Thesis: On Efficient Software Realization of Sequential Machines. Aug 2003 (expected)
M. Sci. Thesis: Multi-valued Logic Network Minimization and its Applications, May 2000
Advisor: Robert K. Brayton

Tsinghua University  (1993-1998)
Beijing China

B. Eng. Microelectronics.
Thesis: Java-based Analog Circuit Optimizer using Genetic Algorithms.
Best B. E. thesis award in the Inst. of Microelectronics, Tsinghua Univ. 1998

Professional Experience

Graduate intern (Jul.2002-Oct.2002)
IBM T.J. Watson Research Center, Yorktown Heights, NY
Researched system-on-Chip power behavior analysis by power state modeling and symbolic simulation.

Mayfield Fellow (May.2001-Aug.2001)
Teja Technologies Inc., San Jose, CA
Mayfield Fellows Program organized by Mayfield Fund and Haas Business school, for promoting high-tech entrepreneurship and innovation. I was involved in product and marketing strategy development at Teja Technologies, one of Mayfield portfolio companies.

Graduate intern (May.2000-Aug.2000)
Cadence Berkeley Lab., Cadence Design Systems, Inc.
Researched software synthesis methodologies and optimization algorithms for embedded control systems.

Graduate intern (May.1999-Jul.1999)
Magma Design Automation Co. Cupertino, CA
Developed algorithms for timing optimization of large hardware systems

Academic Experience

Graduate Student Instructor ( Spring 2000, Spring 2002)
University of California, Berkeley
Assisted graduate course EECS219B on logic synthesis and verification given by Dr. Andreas Kuehlmann in Spring 2002, and by Prof. Robert Brayton in Spring 2000. Gave discussion lectures; designed homework and midterms. Mentored and advised over 10 class projects, some of which led to workshop and symposium publications. (student evaluations conducted by Eta Kappa Nu)

Graduate Student Researcher  (Aug. 1998-Now)
University of California, Berkeley
Projects involved:
MVSIS: Multi-valued logic synthesis and its applications, main contributor and software architect. Version 2.0 released Jun. 2003. Nexsis: next generation hardware synthesis, studied chip-level physical assembly problem. BACPAC: a web-based Berkeley Advanced Chip Performance Calculator, implemented its computing engine and web-interface. Software accessible here. Other class projects include Satre: a Boolean Satisfiability-based VLSI area router, ProSyn: protocol converter synthesis from a control synthesis approach, and MinSyn: macro instruction synthesis for embedded RISC processors.

Publications

Activities

Paper review for DAC 2001-2002, ICCAD 2001-2002, IWLS 2000-2002

Donald O. Pederson Electronic Systems Design Seminar co-organizer, 2001

Mayfield Fellows Program, Berkeley Fellow, 2001

UC Berkeley Business Plan Competition participant, 2001

IEEE student member since 1998

CalBlue soccer team member since 1998

Awards

Best B. E. thesis award in the Inst. of Microelectronics, Tsinghua Univ. 1998

Award for Excellent Student of Tsinghua Univ. 1995-1997

Skills

Programming : Java, C, C++, PERL, Tcl/Tk on UNIX & PC platform

Software : Matlab, SPICE, Word, Power Point.

Communication : Effective oral presentation and technical writing skills.