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Automating the Drudgery in Systems-on-Chip DesignAbstractDesigning a system-on-chip (SoC) today is a labor intensive, error-prone and time consuming process. Even if pre-designed and pre-verified intellectual property (IP) blocks are used, assembling an SoC using such blocks still requires designers to understand the functionality, interfaces and electrical characteristics of complex cores such as microprocessors, bus arbiters, DMA controllers, etc. The designer is forced to spend a significant amount of time in activities other than optimization and verification of the system. SoC design today is at a stage similar to logic design prior to hardware description languages and automatic logic synthesis. New methodologies and tools are required in order to transform the SoC design process into a fully automated task which relies on high- levels of abstraction and automatic system synthesis tools. This talk gives an overview of the main steps in SoC design from a high-level component integration point of view and present new SoC design approaches being researched at IBM. |