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Interconnect Performance: An Architectural View
AbstractA novel way of mapping equivalent communication distance versus equivalent delay yields an intuitive way of viewing interconnect performance across multiple process generations. In this talk, the architectural communication maps for four process roadmaps (one of which is the ITRS99 Roadmap) give insight into how process improvements may affect traditional EDA problems, depending on one's perspective on technological improvement, and bound the impact of scaling on interconnect performance. While low-k dielectrics may potentially yield improvements that offset scaling increases in RC delay, the impact on coupling noise is often only anecdotally studied. The second part of this talk presents an argument for why we should be vigilant in our consideration of noise as a part of interconnect performance, as well as initial simulation results that assess coupling noise for the four roadmaps. |