Slides and handouts for various sessions:

• Session1 : Introduction to VIS
  • Powerpoint slides (slide show)
  • Postscript file

• Session2 : Getting to know VIS
  • Lab instruction in Postscript
  • Verilog/CTL files in tar.gz format

• Session3 : Formal Verification vs Simulation
  • Powerpoint slides (slide show)
  • Postscript file

• Session4 : Lab - Verification
  • Lab instruction in Postscript
  • Lab Solution in Postscript
  • Verilog/CTL files in tar.gz format

• Session5 : Model Checking
  • Powerpoint slides (slide show)
  • Postscript file

• Session6 : Lab - Model Checking
  • Lab instruction in Postscript
  • Lab Solution in Postscript
  • Verilog/CTL files in tar.gz format

• Session7 : Fairness Constraints
  • Powerpoint slides (slide show)
  • Postscript file

• Session8 : Lab - Fairness Constraints
  • Lab instruction in Postscript
  • Verilog/CTL files in tar.gz format

• Session9 : Overview of the Project
  • Powerpoint slides (slide show)
  • Postscript file

• Session10 : Computational and Efficiency Issues in VIS
  • Powerpoint slides (slide show)
  • Postscript file

• Session10B : Lab - Computational and Efficiency Issues in VIS
  • Lab instruction in Postscript
  • Verilog/CTL files in tar.gz format

• Session11 : Lab - Project
  • Lab instruction in Postscript
  • Verilog/CTL files in tar.gz format

• Session14 : Software Engineering
  • Postscript file