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System-level Timing Analysis
and Memory Estimation for Core Based
Network Processor Design
Samarjit Chakraborty
ETH, Zurich
Monday, September 30, 2002, 4:00pm-5:00pm
540AB Cory Hall (DOP Center Classroom)
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Abstract
Increasingly SoCs are being designed using intellectual
property blocks, or cores, which are connected together by buses based
on standard architectures such as CoreConnect or AMBA. An emerging option
for integrating such cores is also to use on-chip networks. However, currently
there are almost no high-level methods/tools to analyse such designs easily.
This, to a large extent, defeats the goals of reuse and easy plug-and-play
which motivate such designs. In this context, I shall talk about an analytical
performance model for such core based SoC designs for implementing a network
packet processor. This model can be specifically used estimate, on a system-level,
on-chip buffer memory requirements of a design and the delays experienced
by packets from different network flows entering the chip. It is based
on models for packet processing tasks that are implemented on the chip
being designed, a method for characterizing network packet flows, and takes
into account the effects of different scheduling strategies and arbitration
schemes implemented in the different cores and buses. Most of this work
is based on leveraging methods from the area of communication networks.
I shall also briefly compare the results obtained using this analytical
model with those obtained by detailed cycle-accurate simulations.
This talk represents joint work with Simon Kuenzli
and Lothar Thiele from ETH Zurich, Matthias Gries from UC Berkeley, and
Patricia Sagmeister and Andreas Herkersdorf from IBM Research Zurich.
Speaker
Samarjit Chakraborty is a PhD student, working with the Computer Engineering and Networks Lab at ETH Zurich. Prior to joining the ETH, he studied Computer Science and Engg. at the Indian Institute of Technology
Kanpur, from where he obtained a Master's degree in 1998. He received his
Bachelor's degree in the same subject from Jadavpur University, Calcutta,
in 1996. His current research is in the areas of real-time embedded systems and computer networks.
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