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Program-In, Chip-Out: The HP
Labs Automatic Hardware Synthesis Project
Rob Schreiber
HP Labs, Palo Alto, CA
Monday, October 7, 2002, 4:00pm-5:00pm
540AB Cory Hall (DOP Center Classroom)
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Abstract
Chip designers are called on
to design an ever larger variety of low-cost, low-power, embedded ASICs
able to process high-bandwidth multimedia data streams. Many of these
ASICs use custom hardware accelerators for the computational "hot spots."
Design time, cost, energy consumption, and performance are important in
these designs. As Moore's Law and the growth of the industry outstrip
our ability to create and debug such designs by hand, automatic ASIC design
has become a hot topic. In order to reduce design time and design
cost, the HP Labs Program-In, Chip-Out (PICO) project focuses on automatic
design from high-level specifications. Source code (in a subset of
C) for a performance-critical loop nest is used as a behavioral specification.
The PICO system compiles the source code into a custom hardware design
in the form of a parallel, special-purpose processor array. The user,
or a design exploration tool, specifies the number of processing elements
and their performance. The system produces the array, its local RAM,
its control logic, its interface to memory, and its interface to a host
processor. PICO also modifies the user's application software to
make use of the generated accelerator. In experimental comparisons,
PICO designs are slightly more costly than hand-designed accelerators with
the same performance. In this talk, we give an overview of PICO,
and describe practical solutions to some subproblems that play a major
role -- tiling, scheduling, bitwidth analysis, data path synthesis, local
memory management, and estimation of the number of array elements referenced
in a loop nest.
Speaker
Rob Schreiber is a Principal Scientist at Hewlett Packard
Laboratories. He is known for important basic research in sequential
and parallel algorithms for matrix computation, and compiler optimization
for parallel languages. He was chief scientist and the lead architect
at Saxpy Computer. He was a developer of the sparse-matrix extension
of Matlab, and a leading designer of the High Performance Fortran programming
language. He was one of the developers of the NAS parallel benchmarks.
He wrote the matrix computation libraries at Maspar. At H.P., Rob
has been a technical leader and an implementer of PICO, a groundbreaking
tool for hardware synthesis from high-level specifications. Rob has
taught at Stanford and RPI. He is area editor for scientific computing
of the Journal of the ACM.
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