Dr. Rajeev Murgai

Rajeev Murgai received his B.Tech. from the Indian Institute of Technology Delhi, India in 1987, M.S. from CMU in 1989, and Ph.D. from University of California at Berkeley in 1993. Since 1994, he has been with Fujitsu Laboratories of America, Inc. Currently, he is the Project Leader of the Layout-driven Logic Optimization Group in the Advanced CAD Research Department. His research interests are logic synthesis, performance optimization, physical design, FPGAs, partitioning, and system-level low power issues.

Email: murgai@fla.fujitsu.com