| |
|
|
Electronic Systems Design Seminar
|
|
|
|
|
|
|
FPL is the classification
language used to program the PayloadPlus® network
processor family from Agere Systems. FPL employs a
data driven, pattern matching paradigm usually associated with more abstract,
symbol manipulating languages such as functional languages (e.g., ML, Haskell),
forward chaining production systems (e.g., OPS5, CLIPS), and text processing
languages (e.g., SNOBOL, AWK). Like
these languages, FPL compiles data pattern specifications into run-time
matching structures that recognize pattern-satisfying data. Unlike these
languages, FPL provides patterns and actions appropriate to bit streams
arriving at a network processor's packet classification engine. An FPL compiler
translates patterns into a matching network, implemented in hardware in a
patented access structure that uses conventional RAM, avoiding the costs of
content addressable memory (
Dale Parson is a Consulting
Member of Technical Staff with Agere Systems, having
worked with Agere since its days as part of Western
Electric / Bell Labs in 1979. He holds
a B.S. in Computer Science
from Albright College, Reading, Pa., and M.S. and Ph.D. degrees in C.S. from
Lehigh University. Dale's doctoral research concerned time-constrained pattern
matching in data-driven production systems related to OPS5. His professional
computing focused on CAD tool development for VLSI circuit design in the 80's
and embedded system software tools -- simulators, compilers, distributed
debuggers and profilers -- in the 90's. He is currently a member of Agere's Digital Communication Architectures and Software
Department, performing research on network processing architectures and
algorithms.
