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Simit-ARM: A series of free instruction-set simulators and micro-architecture simulators

SimIt-ARM

Primary Author: Wei Qin (Princeton)
See http://simit-arm.sourceforge.net/ for up to date information.

SimIt is the name of a series of free instruction-set simulators and micro-architecture simulators. The intention of SimIt is to share research infrastructures with colleagues in all fields related to computer architecture.

The first release of the SimIt series is SimIt-ARM: simulators for the ARM architecture. The SimIt-ARM package contains an instruction-set simulator (sometimes called emulator) and a cycle-accurate simulator for the StrongARM architecture. Both simulators read ELF32 little-endian ARM-linux binaries and can simulate most of the SPEC Int and SPEC FP benchmarks. The instruction set simulator was formerly released as Armsim.

SimIt-ARM was developed to demonstrate the usefulness of the Operation State Machine model and the Mescal Architecture Description Language. SimIt-ARM is free software and you may use it under the terms of the GNU General Public License. See the enclosed COPYING file for more information.

SimIt-ARM features:

• Very high simulation speed.
  On a Pentium III 846MHz desktop, the instruction-set simulator runs at above 9.5MIPS, and the cycle-accurate simulator runs at around 1MHz.



• High accuracy.
  The cycle-accudate simulator is calibrated against a Linux based IPAQ PDA containing a SA-1100 chip. The timing accuracy is within 3% for integer benchmarks according to my measurements.



• FPE support.
  The ARM FPE instructions are emulated by the NetWinder FPE library, which reflects the real execution trace on a Linux based ARM platform.



• Auto-synthesized components.
  The binary decoders used in release 1.0 and above are automatically synthesized with high quality and guaranteed correctness (see reference 2). The cycle-accurate simulator in release 2.0 is mostly synthesized from a MADL (Mescal Architecture Description Language) program.



• Multi-processor simulation support.
  Release 1.1 and beyond supports multi-processor simulation. More than one emulator or simulator instances can be created at the same time. Moreover, in relase 2.0, the processor core can communicate with external devices through either memory mapped means or comminication APIs.

The structure of the instruction set simulator resembles that of the powerpc emulator written by Gilles Mouchard. Simplescalar was also used for reference and validation. The cycle accurate simulator is based on the Operation State Machine formalism (see reference 1).

Sourceforge download page

With the help of Artur Klauser, the speed of the instruction set simulator (ISS) of release 2.0.2 can improve by 20% if configured with the --enable-mmap switch. The result of the switch is that 4MB memory pages will be used for emulation, instead of the default 4KB pages. Release 2.0 and later features the fastest cycle-accurate simulation speed for StrongARM. Its speed almost doubles that of all previous releases. The secret of the blazing speed is the Mescal Architecture Description Language. The cycle-accurate simulator is mostly synthesized from a description in MADL (check out simulator/src/).

To build ARM-linux binaries, you need a cross-compiler. The simplest way to obtain such a compiler is to download prebuilt binaries from here. But if you don't have the permission to install RPMs on your system, or if you prefer trying the hard way, you can build the cross-compiler yourself. See here for building instructions. Note that you should avoid using the cross-compiler distributed along with the simplescalar ARM target. That cross-compiler utilizes header files from some possibly old linux kernel, which is not compatible with SimIt-ARM (The problem is related to the definition of the stat structure).

Download some prebuilt benchmarks benchmarks.tar.bz2(6.25MBytes).

Feedback or contributions are welcome!

Reference:

1. Wei Qin, Sharad Malik. Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation. Design, Automation, and Test in Europe (DATE), March, 2003.
2. Wei Qin, Sharad Malik. Automated Synthesis of Efficient Binary Decoders for Retargetable Software Toolkits. DAC'03, June, 2003.

MADL: Mescal Architecture Description Language

MADL

Primary Author: Wei Qin (Princeton)

MADL is the Mescal Architecture Description Language.

madl-1.0a.tar.gz The specification of MADL, its compiler and example description for StrongARM.
madl-1.0a is a test release for experts who understand the concept of OSM and MADL.
madl-1.0a was first released on September 15, 2003.

ARMn: A Multiprocessor Cycle-accurate Simulator

Primary Author: Xinping Zhu (Princeton)

(Not actively maintained, for reference only)

ARMn is a multiprocessor cycle-accurate simulator which can simulate a cluster of ARM processor cores connected by custom communication schemes, such as wormhole based packet-switching, fully connected crossbar switches or regular standalone buses. The topology supported include mesh, torus and star shape.

The PE model used by ARMn is based on works by Wei Qin, who developed a fast ARM simulator SimIt-ARM.

The communication part is written in SystemC which wraps the PE model around and enables it to communication with other communication modules (also written in SystemC).

The minimum requirement for installing ARMn are a Redhat 7.0 box on X86 with SystemC libraries and C++ compilers.

Key Features and Highlights

1. A C/C++ (SystemC) written cycle-accurate communication architecture simulator.
2. A library of reusable communication modules such as buffers (channel), arbiters and crossbars.
3. Fully integrated with an accurate ARM PE model. Can simulate message passing based application binaries compiled by crosscompilers.
4. Fast Simulation Speed. (> 10K cycles per second for a 9PE cluster)
5. Designed for Fast Prototyping and Validation

Download

armn-sim.tar.gz - ARMn-0.2, released November 16th, 2003

README.armn - from ARMn-0.2

Reference

X.Zhu, S.Malik, "Using A Communication Architecture Specification in an Application-driven Retargetable Prototyping Platform for Distributed Processing", Proceedings of 2004 Design Automation and Test in Europe Conference (DATE 04), Feb, 2004 (Pre-print pdf )

• README_armn.txt · View · Download · 3 kbytes
• armn-sim.tar.gz · View · Download · 6875 kbytes

CoreConnect Model: A cycle-accurate IBM CoreConnect model using Operation State Machines (OSMs)

Primary Author: Xinping Zhu (Princeton)

CoreConnect is a complete model tookit which can model and simulate 32-bit IBM CoreConnect Bus Architecture using Operation State Machine (OSM) models.

The concurrency model - the OSM - is based on works by Wei Qin, who developed a fast ARM simulator SimIt-ARM.

The specification we used in this study is based on

1. IBM 32-bit Processor Local Bus Architecture Specification Version 2.9. coreconnect_32bit.pdf
2. PLB Functional Model Toolkit, Chap 6, PLB Bus Functional Language coreconnect_bfl.pdf

The Official IBM CoreConnect Website : http://www-306.ibm.com/chips/products/coreconnect/

Key Features and Highlights

1. A C/C++ written cycle-accurate coreconnect bus model and its corresponding description.
2. A library of reusable communication modules such as timers, arbiters, etc.
3. Fast Simulation Speed. (> 200K cycles per second for a 4 node bus architecture on a P4 with Linux )

Download

coreconnect-rel-0.1.tar.gz .

View README.cc.txt .

Reference

X.Zhu, W. Qin, S. Malik, Modeling Operation and Microarchitecture Concurrency for Communication Architectures with Application to Retargetable Simulation , Proceedings of International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS), Sep, 2004(PDF, Powerpoint)

X.Zhu, S.Malik, "Using A Communication Architecture Specification in an Application-driven Retargetable Prototyping Platform for Distributed Processing", Proceedings of 2004 Design Automation and Test in Europe Conference (DATE 04), Feb, 2004 (PDF )

Wei Qin, Sharad Malik. Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation. Design, Automation, and Test in Europe (DATE), March, 2003.

W. Qin, Mescal Architecture Description Language 1.0, Draft.

• coreconnect.gif · View · Download · 13 kbytes
• README.cc.txt · View · Download · 6 kbytes
• coreconnect_32bit.pdf · View · Download · 671 kbytes
• coreconnect_bfl.pdf · View · Download · 946 kbytes
• coreconnect-rel-0.1.tar.gz · View · Download · 1184 kbytes