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Bryan Catanzaro

Bio:

Bryan Catanzaro is a PhD student in EECS at the University of California, Berkeley. He received the B.S. in Computer Engineering and Russian in 2003, and the M.S. in Electrical Engineering in 2005, both from Brigham Young University. He is a student member of IEEE.

Abstract:

A major shift towards heterogeneous multiprocessor systems-on-chip is now in progress. Despite decades of research into parallel computing, the general computing world would much rather continue using serial programming models because of their ubiquity and ease of use. However, power efficiency problems and poor interconnect scaling have forced the industry towards multiprocessor platforms-on-chip. Today's multiprocessor platforms, such as Graphics Processing Units, Network Processors, and multi-core general purpose processors, have between 2 and tens of processors on a die. Tomorrow's multiprocessor platforms will have richer, more heterogeneous computing resources, with hundreds or thousands of processing elements on a single die.

Compounding this parallel programming problem is the worsening memory latency "wall", as well as the exorbitant costs of keeping memory coherent in a large multiprocessor system. State-of-the-art multiprocessor platforms (such as STI's Cell processor and the Intel IXP 2000 family) are trending towards towards diverse memory hierarchies which do not preserve the illusion that all processes have uniform access to a single pool of memory.

Programming such platforms requires new approaches which preserve parallelism through all stages of computation, while allowing the programmer to make effective use of heterogeneous compute and memory resources. Much work in this area has already been done - we are therefore beginning our investigation into this problem by examining various programming environments for the Intel IXP 2000 family, such as Atlatl, Teja NP, and PacLang, to discover the strengths of each approach to the multiprocessor programming problem. In the near future, we also will be examining programming models for digital signal processing and media applications on soft-core multiprocessor systems.

The overall goal of our research is to identify what abstractions and automated tools are necessary to enable the efficient exploitation of future programmable multiprocessor platforms.

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