KSPICE

KSPICE is a circuit simulator based on SPICE3E2, with improved transient analysis of lossy transmission lines. Unlike SPICE3, which uses the state-based approach to simulate lossy transmission lines, KSPICE simulates lossy transmission lines and coupled multiconductor line systems using the recursive convolution method. The impulse response of an arbitrary transfer function can be determined by deriving a recursive convolution from the Pade approximations of the function. We use this approach for simulating each transmission line's characteristics and each multiconductor line's modal functions. This method of lossy transmission line simulation has proven to give a speedup of one to two orders of magnitude over SPICE3E.

The new device models of KSPICE are TXL and CPL, for modeling a single lossy transmission line and a coupled multiconductor line system, respectively. These device models can effectively replace the current LTRA model of SPICE3. The model LTRA is included in the current release of KSPICE merely for comparison purposes.

The implementation of the transmission line simulation of KSPICE is based on that of SWEC. However, SWEC lacks the capability of handling analog circuits as well as many of the functionalities of SPICE3. KSPICE, on the other hand, encompasses the full functionality of SPICE3 and provides a very fast and accurate lossy transmission line simulation.

Hardware/Operating System Requirements: UNIX (Ultrix 4.0, SunOS 4.0, HPUX 7.0 or AIX 3.1)

Compiler: C compiler for MS-DOS

Versions Available: UNIX

Distribution Media: QIC-120, QIC-150, QIC-320, 8mm (2.2 gig), TK50 (DEC tape format), 9-track 1600 bpi, 9-track 6250 bpi.

Source Code: Yes

Object Code: No

Materials/Handling Fee: $250.00

Documentation Included with the Program:

1. KSPICE User's Manual and Installation Notes. Available separately for $5.00

Additional Documentation Available:

1. S. Lin and E. S. Kuh, "Pade Approximation Applied to Transient Simulation of Lossy Coupled Transmission Lines," Proc. IEEE Multi-Chip Module Conference, 1992, pp. 52-55. $5.00
2. S. Lin, M. Marek-Sadowska, and E. S. Kuh, "SWEC: A StepWise Equivalent Conductance Timing Simulator for CMOS VLSI Circuits," European Design Automation Conf., February 1991, pp. 142-148. $5.00
3. S. Lin and E. S. Kuh, "Transient Simulation of Lossy Interconnect," Proc. Design Automation Conference, Anaheim, CA, June 1992, pp. 81-86. $5.00

Foreign Distribution: Yes