A Case Study on Modeling Shared Memory Access Effects during Performance Analysis of HW/SW Systems
Abstract:
Behavioral simulation with timing annotations derived from performance
modeling and analysis is a promising alternative for use in evaluating
system-level design tradeoffs.
The accuracy of such approaches is determined by how well the effects
of various HW and SW architectural features, like the Real Time
Operating System (RTOS), shared memories and buses, HW/SW
communication mechanisms, etc are modeled at this level.
We present a study of the effects of shared memory buses during
system-level performance analysis in the POLIS co-design
environment, using the example of a TCP/IP Network Interface
System. We demonstrate how the effects of the memory
arbiter and shared memory bus can be modeled efficiently at the
behavioral level, and used to evaluate various design
tradeoffs. Experimental results demonstrate that modeling these
effects can significantly increase the accuracy of system-level
performance estimates.
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