VLSI Scaling Issues


Abstract

As architectural complexity grows and clock cycle times shrink, VLSI implementation constraints are becoming an increasing important issue for processor research. Unfortunately, the capability and constraints of the underlying technology is often misunderstood, especially when it comes to the relative speed of gates and wires. At first glance, the future of wires in integrated circuit technologies looks grim. Even projections with copper interconnections and low-k dielectrics show that wire delay for a fixed length wire will increase at a rate that is greater than linear with scaling factor. This has led to a number of papers which have predicted the demise of the world as we know it.

This talk examines historical processor performance scaling, and relates the performance gains to changes in architecture, circuit design, and technology. It then examines gate and wire scaling to get a better idea of what will happen in the future. The results are a little surprising. If an existing circuit is scaled to a new technology, the relative change in the speed of wires versus the speed of gates is modest. Depending on the assumptions on transistor performance under scaling, low-k dielectrics, and higher aspect ratio wires, the ratio is close to one. That does not mean scaling is not without problems. The two main challenges a designer faces are the decreasing numbers of gates allowed in each clock cycle, and the delay of the global wires in the machine. The latter are the wires that don't scale in length as the technology shrinks because the machine got more complicated. These wires are a problem.

Presentation Slides (pdf)
Related Paper (pdf)


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