Dr. Desmond Kirkpatrick

Desmond Kirkpatrick received the Ph.D. degree from UC Berkeley in December, 1997 as a graduate researcher with Professor Sangiovanni-Vincentelli as his advisor. His research culminated in his dissertation entitled "The Implications of Deep Sub-micron Technology on the Design of High Performance Digital VLSI Systems". He previously received the SBEE degree from MIT in 1986, with his thesis entitled "Simulation of the RC Mesh".

From 1986-1991, he worked as a CAD engineer in the Design Technology group at Intel Corporation where he made significant contributions in hierarchical, full-chip timing analysis, floor-planning, layout synthesis, and RC extraction for the 486 and Pentium microprocessors. In 1990, he led a team investigating high-level modeling techniques.

From 1991 to 1995 he was a member of the Pentium Pro design team and from late 1997 through 1999 he was a member of a high-performance IA-32 design team. On both teams he contributed to full-chip assembly and interconnect performance management techniques, especially addressing noise concerns. He contributed to the specification of the interconnect architecture for Intel's next-generation process technology. He is presently Intel's technical liaison to the Gigascale Semiconductor Research Center.

Desmond has interests in signal integrity, layout and logic synthesis, formal verification, and high speed circuit design. He has several publications in the areas of logic synthesis, floorplanning, routing, and formal verfication.

Email address: desmond@ic.eecs.berkeley.edu