Dr. Kaustav Banerjee

Kaustav Banerjee received the Ph.D. degree in Electrical Engineering and Computer Science from the University of California at Berkeley in 1999 for his research on modeling thermal effects in deep sub-micron VLSI interconnects and their implications for circuit performance and reliability.

Since March 1999, he has been with Stanford University as a Research Associate, with joint appointments from the Integrated Circuits Lab-Electrical Engineering Department, and the Thermosciences Division-Mechanical Engineering Department. He is also a member of the MARCO Interconnect Technology Focus Center at Stanford. His broad area of research interest lies in performance analysis, thermal modeling, and reliability issues in high-speed VLSI interconnects, RF, and novel circuit architectures including 3-D multilayer ICs.

At Stanford, Dr. Banerjee co-mentors nine doctoral students and leads an interdisciplinary research team (at the Center for Integrated Systems) that focuses on a number of different thermal design, performance, and reliability issues for deep sub-micron VLSI interconnects and circuits, RF, and emerging circuit architectures like 3-D multilayer ICs. This effort includes development of accurate device and circuit level electro-thermal models and CAD techniques, novel microscale thermal characterization methods and high-performance cooling techniques.

He has held several summer research positions at the Semiconductor Processing and Device Center of Texas Instruments Inc., Dallas, during 1993-1997. He has authored or co-authored over 25 research publications in archival journals and refereed international conferences, including several invited talks and tutorials. He has also served as a member of the technical program committee for the IEEE EOS/ESD Symposium 2000.

Email address: kaustav@holst.stanford.edu