Incremental Block-Level Silicon Compilation Methodology for Deep Sub-micron ASICs: An Object-Oriented Approach

Abdallah Tabbara

Objective

It is generally agreed within the EDA community [5] that Deep Sub-Micron (DSM) semiconductor technology is forcing major discontinuities in traditional design methods. The complexity and scale of integration, as well as the significant cost of design errors, promotes a re-evaluation of design practice and an increase in "co-design" early in the design process.

In this work, we lay the groundwork for a new design system that exploits both a recently proposed methodology [1] for performing logic and physical design in parallel [4] in a non-iterative fashion [11], using object-oriented modeling and component based schemes for design specification. The method allows for incremental design exploration and refinement at all levels of abstraction and permits the rapid characterization of the final placed and routed design block by block, and object by object. For a more detailed description of the methodology the reader is referred to the following discussion.

Progress and Status

We have been able to lay the groundwork for implementing a block level object-oriented silicon compiler [2] that takes as input Java code [8], extracts the object decomposition, and generates a structural layout at the gate level, that can be debugged visually just like software code to allow for rapid iteration between the front and back ends.

More recent efforts have been directed towards accomplishing two goals. The first is to create a "real" design example that would serve as a testbed for experimenting with the JavaTime design and specification system and with the possible ways that the backend might fit into this framework. To this end we participated in prepared a demo for DAC'98 for JavaTime. The example that was picked as best suited for this task is a software implementation of an MPEG2 encoder. The bulk of the work included porting about 7 thousand lines of C code to Java then changing the code to conform with the JavaTime Component Package specification and simulating a few test examples.

On the other hand, in order to better understand the issues involved in the new design methodologies being suggested [11], we studied the problem of retiming with area delay trade-offs and delay constraints in a new non-iterative approach [11]. Initial results show that a reinterpretation of classical algorithms to solve this problem are needed. The resulting algorithms will be included in the tool which is being developed.

Future Work

This project will serve as a proof of concept for the object-oriented block level silicon compilation approach, and will help us refine our ideas into a more general scheme and system that can handle a larger subset of the input language if needed, and potentially interface to commercial CAD tools [7].

A more detailed list of milestones includes:

References

  1. Eory, F. "Systems to Silicon Design: Methodology for Deep Sub-micron ASICs", SuperCon, 1997
  2. Mead, C. et. al. "Introduction to VLSI systems" Addison-Wesley, 1980
  3. McLeod, J. "Silicon Compilation Strikes a Chord", Integrated Systems and Design Magazine, 1997
  4. Newton, A. R. Personal Communication, 1997
  5. "National Technology Roadmap for Semiconductors", Semiconductor Industry Association, 4300 Stevens Creek Blvd., Suite 271, San Jose, CA 95129, phone: (408) 246-2711.
  6. Rumbaugh, J. "Object-Oriented Modeling and Design" Prentice Hall, 1991
  7. Sentovich, E. M. et. al. "Sequential Circuit Design Using Synthesis and Optimizations" ICCAD, 1992
  8. Sun Mircosystems, Inc. "Java Virtual Machine Specification", 1997
  9. Young, J. S. Tabbara, A. Newton, A. R. et. al. "Design and Specification of Embedded Systems in Java Using Successive, Formal Refinement" DAC, 1998
  10. Zhou, X. "Building Blocks and their Interactions" IEEE Potentials Magazine, October 1997
  11. Otten, R.H.J.M. Brayton, R.K. "Planning for Performance" DAC, 1998

Please send comments to: Abdallah Tabbara (atabbara@ic.eecs.berkeley.edu)