Abdallah Tabbara, Graduate Student
(Professor Robert K. Brayton) (Professor A. Richard Newton)
Funding Sources: GSRC, SRC contract 98-DC-324, California MICRO Program,
The conventional VLSI design flow consists of an integration of various steps and tools in order to synthesize a circuit. Typically the flow introduces a separation between the logic synthesis step and the physical design step. For designs with aggressive performance goals, this division entails hundreds of iterations between synthesis and physical design before converging to the desired implementation and achieving closure on design constraints, especially timing. In this work we address this issue and lay the groundwork for a new design flow that exploits (a) the recently proposed idea of planning for performance [1] at the early stages of the flow in order to minimize design iteration, (b) recent work in the area of retiming [2], and (c) results of a recent study of delays in DSM [3]. The retiming work promises to permit area and delay trade-off decisions at the early stages of floor planning. In this work, we introduce retiming into the architectural floorplanning stage, and show how it has the potential to address and provide solutions to timing closure issues in deep sub-micron [3].
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