A Top-Down Design Methodology for Analog Circuits and Systems

The objective of this project is to expand the domain of applicability of the top-down ,constraint-driven design methodology, introduced by the analog CAD group, into larger analog systems. The methodology is fully described in [Chang92], and its advantages have already been discussed and substantiated by results [ChangCICC94]. The key points of this methodology are:

top-down hierarchical process starting from the behavioral level based on early verification and constraint propagation;

bottom-up accurate extraction and verification;

automatic and interactive synthesis of components with specification constraint-driven layout design tools;

maximum support for automatic synthesis tools to accommodate users of different levels of expertise but not the enforcement of these tools upon the user; this is not an automatic synthesis process;

and consideration for testability at all stages of the design.

Current research

The top-down methodology has been applied to the design of a system which synthesizes the clock and RGB currents required for high resolution monitors. The system includes a frequency synthesizing Phase-Locked Loop (PLL) and three current source DACs, as well as digital registers and logic circuits. A principal part of this project has been the design of the PLL, which can be also used in other types of systems , such as communication tranceivers. The basic architecture selected for the PLL consists of a Phase-Frequency Detector, a Charge Pump , a Loop Filter and a Voltage-Controlled Oscillator (VCO). Three frequency dividers are being used, one after the reference crystal oscillator , one inside the feedback loop and one after the output of the VCO, so that a different number of frequencies can be generated.

The PLL performance constraints , which consist of the PLL's frequency range and timing jitter , are mapped by using a modified version of behavioral simulation tools introduced in [DemirCICC94], onto component values for the loop filter, delays of the digital circuits and finally the voltage to frequency gain and the timing jitter of the VCO. The algorithm used for the optimization is based on the Supporting Hyperplane algorithm.

At the lower level, the VCO constraints are being mapped onto device sizes. The VCO has also been designed using optimization at circuit level, having as constraints the frequency range , the voltage frequency gain , the maximum allowed deviation allowed from the nominal gain, and the timing jitter. The objective of the optimization is to minimize the dissipated power. The constraints are checked by a circuit simulator except for the jitter which is checked by equations. The verification for the timing jitter is being done by using the simulation techniques discussed in [DemirICCAD94].

The layout is done in a Constraint -Driven mode too, using sensitivity analysis to generate constraints for parasitics and giving the results to a layout generation tool. The chip has been fabricated in a 1.0u process and performance has been verified.

The design of the above system was a joint project with Henry Chang. The cooperation of Edoardo Charbon and Alper Demir are also greatly appreciated.

References

[Chang92] H.Chang, A.Sangiovanni-Vincentelli, F.Balarin, E.Charbon, U.Choudhury, G.Jusuf, E.Liu, E.Malavasi, R.Neff, and P.Gray, ``A Top-down, Constraint-Driven Design Methodology for Analog Integrated Circuits'', in Proc. IEEE Custom Integrated Circuits Conference, pp. 841--846, May 1992.

[ChangCICC94] H. Chang, E. Liu, R. Neff, E. Felt, E. Malavasi, E. Charbon, A.Sangiovanni-Vincentelli, and P.R.Gray, ``Top-Down, Constraint-Driven Design Methodology Based Generation of n-bit Interpolative Current Source D/A Converters,'' in IEEE Custom Integrated Circuits Conference, May 1994.

[DemirCICC94] A.Demir, E.Liu, A.Sangiovanni-Vincentelli and I. Vassiliou, ``Behavioral Simulation Techniques for Phase/Delay-Locked Systems,'' in IEEE Custom Integrated Circuits Conference, May 1994.

[DemirICCAD94] A. Demir, E. Liu and A.L. Sangiovanni-Vincentelli, "Time-Domain non-Monte Carlo Noise Simulation for Nonlinear Dynamic Circuits with Arbitrary Excitations", Proc. IEEE ICCAD, San Jose, November 1994.

Future research

We are planning to apply this methodology in the design of RF systems