Phil's Publications

http://www-cad.eecs.berkeley.edu/~pchong/publish.html

• M. Prasad, P. Chong and K. Keutzer, "Why is Combinational ATPG Efficiently Solvable For Practical VLSI Circuits", Journal of Electronic Testing: Theory and Applications, Vol 17, No 6, Dec 2001, pp 509-527.
• P. Chong and R.K. Brayton, "Characterization of Feasible Retimings", Tenth International Workshop on Logic Synthesis, Jun 2001, pp 1-6.
• P. Chong, Y. Jiang, S. Khatri, F. Mo, S. Sinha, and R.K. Brayton, "Don't Care Wires In Logical/Physical Design", Ninth International Workshop on Logic Synthesis, Jun 2000, pp 1-9.
• M. Prasad, P. Chong and K. Keutzer, "Why is ATPG Easy?", Proceedings of the 36th Design Automation Conference, 1999, pp 22-28.
• P. Chong and R.K. Brayton, "Estimating and Optimizing Routing Utilization in DSM Design", Workshop on System-Level Interconnect Prediction, 1999.
• P. Chong, M. Prasad, and K. Keutzer, "Why is ATPG Easy?", ERL Memorandum UCB/ERL M99/9, UC Berkeley, Feb 1999.
• T.J. Callahan, P. Chong, A. DeHon and J. Wawrzynek, "Fast Module Mapping and Placement for Datapaths in FPGAs", Proceedings of the Sixth International Symposium on Field Programmable Gate Arrays, 1998, pp 123-132.
• P. Chong and W.M. Loucks, "Simulation of Queueing Systems in FPGAs", Proceedings of the 4th Canadian Workshop on Field-Programmable Devices, 1996, pp 156-161, University of Toronto.
• P. Chong, "A Digital Cosimulation Platform", Technical Report, E&CE Department, University of Waterloo, 1995.
• P. Chong, "Power Consumption in FPGAs", Technical Report, Teklogix Inc., 1994.