Conference Publications


Vigyan Singhal, Sharad Malik, Robert K. Brayton. The Case for Retiming with Explicit Reset Circuitry. In Proc. of Intl. Conf. on Computer-Aided Design, San Jose, CA, November 1996.

Shaz Qadeer, Robert K. Brayton, Vigyan Singhal, Carl Pixley. Latch Redundancy Removal without Global Reset. In Proceedings of International Conference on Computer Design, Austin, TX, October 1996.

Adnan Aziz, Kumud K. Sanwal, Vigyan Singhal, Robert K. Brayton. Verifying Continuous Time Markov Chains. In Proc. of Conference on Computer-Aided Verification, New Brunswick, NJ, July 1996.

Thomas R. Shiple, Vigyan Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. Analysis of Combinational Cycles in Sequential Circuits. In Proc. of Intl. Symposium on Circuits and Systems, Atlanta, GA, May 1996.

Adnan Aziz, Robert K. Brayton, Felice Balarin, Vigyan Singhal. Timing-Safe Replaceability for Combinational Logic. In Proceedings of TAU 1995, Seattle, WA, November 1995.

Gitanjali M. Swamy, Robert K. Brayton, Vigyan Singhal. An Incremental Approach to FSM Traversal. In Proceedings of International Conference on Computer Design, Austin, TX, October 1995.

Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K. Brayton. Exploiting Power-up Delay for Sequential Optimization. In Proc. of European Design Automation Conference, Brighton, Great Britain, September 1995.

Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. It Usually Works: the Temporal Logic for Stochastic Systems. In Proc. of Conference on Computer-Aided Verification, Liege, Belgium, July 1995.

Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton. The Validity of Retiming Sequential Circuits. In Proc. of Design Automation Conference, San Francisco, CA, June 1995.

Vigyan Singhal, Carl Pixley, Robert K. Brayton. Power-up Delay for Retiming Digital Circuits. In Proc. of Intl. Symposium on Circuits and Systems, Seattle, WA, May 1995.

Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton. Multi-level Synthesis for Safe Replaceability. In Proc. of Intl. Conf. on Computer-Aided Design, San Jose, CA, November 1994.

Adnan Aziz, Vigyan Singhal, Gitanjali M. Swamy, Robert K. Brayton. Minimizing Interacting Finite State Machines: A Compositional Approach to Language Containment. In Proc. of Intl. Conf. on Computer Design, Cambridge, MA, October 1994.

Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. Equivalences for Fair Kripke Structures. In Proc. of Intl. Colloquim on Automata, Languages and Programming, Jerusalem, Israel, July 1994.

Vigyan Singhal and Carl Pixley. The Verification Problem for Safe Replaceability. In Proc. of Conference on Computer-Aided Verification, Stanford, CA, June 1994.

Adnan Aziz, Thomas R. Shiple, Vigyan Singhal, Alberto L. Sangiovanni-Vincentelli. Formula-Dependent Equivalence for CTL Model Checking. In Proc. of Conference on Computer-Aided Verification, Stanford, CA, June 1994.

A. Aziz, F. Balarin, S.-T. Cheng, R. Hojati, T. Kam, S.C. Krishnan, R.K. Ranjan, T.R. Shiple, V. Singhal, S. Tasiran, H.-Y. Wang, R.K. Brayton, A.L. Sangiovanni-Vincentelli. HSIS: A BDD-based Environment for Formal Verification. In Proc. of Design Automation Conference, San Diego, CA, June 1994.

Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton. Heuristic Minimization of Synchronous Relations. In Proc. of Intl. Conf. on Computer Design, Cambridge, MA, October 1993.

T. Shiple, A. Aziz, F. Balarin, S.-T. Cheng, R. Hojati, T. Kam, S. Krishnan, V. Singhal, H.-Y. Wang, R. Brayton, A. Sangiovanni-Vincentelli. Formal Design Verification of Digital Systems. In Proc. SRC TECHCON, Atlanta, GA, September 1993.

Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton. Heuristic Minimization for Synchronous Relations. In Workshop Notes of Intl. Workshop on Logic Synthesis, Tahoe City, CA, May 1993.

Ellen M. Sentovich, Vigyan Singhal, Robert K. Brayton. Multiple Boolean Relations. In Workshop Notes of Intl. Workshop on Logic Synthesis, Tahoe City, CA, May 1993.




Technical Reports


Vigyan Singhal and Alan J. Smith. Characterization of Contention in Real Relational Databases. Technical Report CSD-94-801, Computer Science Division, 570 Evans Hall, University of California, Berkeley, CA 94720.

Ramin Hojati, Vigyan Singhal, Robert K. Brayton. Edge-Streett/Edge-Rabin Automata Environment for Formal Verification using Language Containment. Memorandum No. UCB/ERL M94/12, Electronics Res. Lab., Cory Hall, University of California, Berkeley, CA 94720.