EE141 project: Shifter Implementation

Introduction

In this project, you will use many 2-1 multiplexers to build a 8-bit left-shifter. Shifters are essential in the design of the multipliers in the Arithmic and Logic Unit (ALU). In order to handle the multiplication of the binary numbers, shifters must be able to left-shift 8 bit inputs by an amount anywhere from 0 to 7 and zero-extend these numbers.

Goal and Objective

In order to reduce the latency for the ALU to meet the timing requirement, you must design it so that the worst case delay for the shifter can not exceed 5ns and the output for the shifter must have a full swing from Vdd to ground, assuming a 5pF load on each output node. Further speedup could be achieved by upsizing the devices; this, however, results in the increase of the overall area (the overall area is defined as the area of the minimum box surrounding all parts of the layout). In this project, you are going to lay out the shifter in a twin well 3.3 Volt CMOS process with two layers of metal; also, you are expected to optimize the circuit according to the cost function which is the product of the propagation delay (worst case) and the total area (Cost = Area * Propagation Delay).

Procedure

A typical 2-1 mux (Figure 1.1) allows for the selection between two input bits (A and B) depending on the value of S0. For the shifter (Figure 1.2), the input signals are a 8-bit data(SH_IN) and a 3-bit control signal (SHAMT); the output is (SH_OUT).

(Figure 1.1, Schematic view of a 2-1 mux)

(Figure 1.2, Schematic view8 bit left shifter)

Design the Logic

First, you carefully design the logic up to gate level. Then you choose a logic style which will help you reach the goal. Since you are not constrained by the power consumption, you are free to use any style you prefer, including the dynamic CMOS logic in which the clock signal is optional. For example, if you decide to build the mux using static CMOS, you can write down the logic equation and realize it using basic logic blocks like NANDs, NORs or XORs. Finally, a quick Spice or hand analysis can be immediately carried out to estimate the W/L ratios for all the transistors.

Implement the Mux

According to the previous estimate, you layout a single mux using MAGIC and make sure that it passes the DRC test. Then you extract the circuit netlist and spice it so that the timing budget is met and the cost for every mux is reasonable. Notice that, whenever possible, you probably want to reduce the size of diffusions because usually diffusions implies parasitic capacitance.

Place and Route

You hierachically layout the shifter by placing and routing many 2-1 muxes as well as some other necessary logic components. One way of doing it is to place muxes into rows and leave channels between the rows. To avoid the possible short circuit situation, you can run metal 1 in horizontal and run metal 2 vertically (metal1 can cross metal 2 because they are on different layers). You are also required to globally connect the VDD lines and GND lines. Attentions should be paid so that you minimizes the area for the interconnect which will be counted towards the overall area of your design.

In real world, people usually design at the HDL or schematic level. The actual layout view of the cell is stored in a standard cell library and the placement and the routing of the cells are done automaticly using CAD software.

Verification and Optimization

In this step, you need to extract the entire layout and make sure that all the design requirements are met using the SPICE. The last step is to adjust the design variables in the previous steps and make trade-offs between them. The two radical approaches are maximizing the speed and minimizing the area; but most likely, you are going to find a optimum cost point somewhere in the middle.

Extra Notices

If you decide to use cadence tools to do the layout, you must convert the output into Magic format and obey all the design rules in Magic. Also you will not be allowed to use Design Compiler to automaticly generate the layout.

Report

The quality of your report is as important as the quality of your design. One must sell the design by justifying the design decisions and providing all the vital information, while eliminating the unneccessary materials. Organization, conciseness, and completeness are of paramount importance. Use the attached cover sheet and fill in the table; be sure to use the correct units. In addition, you should discuss your overall design philosophy and the important design decisions you made. Include schematics, a plot of your magic layout, and the resulting SPICE outputs and decks. Prove that your alleged results are TRUE by providing the crucial plots (don't forget to mention the input patterns you used to obtain those plots). The total report should not contain more than four pages. You are not allowed to add any other sheets, except for SPICE files or important plots. It should be based on the following outlay:

Page 1: Executive summary, overall design decisions, remarks and motivations

Page 2: Transistor diagram - annotated with transistor sizes and worst-case timing path. Plot showing the functional operation of the cell. Comments.

Page 3: Timing simulation - derive value of worst-case path - comments on the optimizations.

Page 4: Layout of the design + comments - Show obtained area.

Remember, a good report is like a good layout: it should perform its function (convey information) in the smallest possible area with the least delay and energy (to the reader) possible.

Grade decomposition:

RESULT: 30%

CORRECTNESS & LAYOUT: 20 %

CREATIVITY: 10 %

REPORT: 40 %

Due: Thu Oct 22, 1997 by 5pm.

NO EXTENSIONS ACCEPTED!

EECS 141: Digital Integrated Circuits - Fall 1997

Report Cover Sheet

Project #1: 8 bit zero-extended right shifter

2 Person Group Project

Due October 22, 1997

Names

Parameter Value

Units

Cost lambda*lambda*ns
Area lambda*lambda
Worst case delay (tp) ns
Grade
Result
Correctness
Creativity
Report
TOTAL