simulation algorithm

1. analog (time driven)

spice

basically just construct a sparce matrix and solve ODE at transistor level

variable are voltage and current

remark: calculation could be huge and the time can exhausting

2. event driven

verilog, vhdl , RSIM

construct a event list using data structure and put all the event into the list and process the event.

gate level, rtl level or behavoir level, gate level.

logic state as variable 0,1 and propagation delay time also considered to find glitch.

remark: statistically shown that for big digital circuit, only 14 percent of the gate will have event very often. so event driven could be efficient.

3. compiled mode

some other software

compile all the circuit description into a piece of executable code and define initial state and final state. run the code during the cycle and swap pointers pointing to initial state and final state so next simulation could be run using the previous final state.

only state variable is concerned and the intermediate value is not of the interest. (Well, could be!)

cycle based

remark: could be very efficient using native c code

the simulation model now

the vhdl compiler read in vhdl code or description of the gate, mapping into some kind of data structure then run the simulation. assume the simulation is event driven, the global scheduler will need to exchange information with every single gate (some information is missing here). So every time we make the change we have to read in the new vhdl code and create a new global schedular. Not a flexible archtecture.

the proposed simulation model

under the new model, the component is self-contained which means that all the components runs itself. All they care is what input they need and what output they need to deliver. Regardless which internal simulation is used, as long as all the components generated a common input or output, we could have a global schedular to administrate the global behavior and cascade all the components to simulate the global behavior. Imagine toshiba's memory could work with intel's cpu and lsi's mem controller, as long as each of the suppliers delivers a component properly. For running larger task, we could even distribute the component thruout the whole internet for utillize much larger resource available. If the suppliers delivers new model, they simply put it on the server and whole environment still works WITHOUT recompiling. Another point is that we can wrap the collection of the components into a higher level component with its own input and output.

the possible bottle neck or some other problem

the network could slow down the simulation. but we can always download the components and simulate locally.

language of the choice JAVA!!

time table and some term deliverables

start now, I will do literature survey. by the end of the semester, I will have some module written and make the whole enviroment up and running. 1. the main feature of the idea is that the model is selfcontained. so I might start by implement all the module using cycle based simulation. 2. how does the whole thing work? what type of assumption has to be made? what does the ui look like? where to start?