============================================================================ Version 0.4. Patch 1 November 30, 2000 The only change is support for Esterel V5 in strl2shift (more specifically in oc2shift). If you installed a BINARY version, gunzip oc2shift.gz for the appropriate architecture (found in the same ftp directory as the main tar files) in $POLIS/bin. If you installed a SOURCE version, gunzip and untar oc2shift.tar.gz in $POLIS/src/polis (so that it overwrites $POLIS/src/polis/strl2shift/oc2shift) and recompile. ============================================================================ Version 0.4 October 11, 1999 The main changes are in the Ptolemy simulation interface, that now supports multiple processors. In particular: - the UC and PTLUC macros in the Makefile no longer pre-load the clock cycle information for the selected processors. The information is loaded dynamically at run time by Ptolemy (section 9.2). - Each SW CFSM can be mapped to a different CPU, as selected by the resourceName star parameter in Ptolemy (Section 6.1). RTOS and interface CFSM synthesis does NOT understand that yet (multi-processor will be supported in future releases). Section 6.1.5 (entitled "Upgrading netlists produced by POLIS 0.3") lists other differences with respect to previous versions. Please, read it before using Ptolemy on old (pre-0.4) designs. - Simulation time is now in seconds, and all the standard Ptolemy testbench stars can be used (section 6.1). - Software estimates can be refined by using an Instruction Set Simulator (an example ISS for the SPARC processor is included with the release; see section 6.5). - Power analysis (via simulation) can now be carried out (section 6.6). - An instruction cache can now be simulated (section 6.7) - Support for simulation and synthesis based on VHDL (behavioral for simulation, synthesizable for synthesis) is greatly enhanced (sections 6.3 and 6.4). - A self-guiding tutorial on using formal verification techniques with POLIS is now included, in directory $POLIS/examples/formal_verification. ============================================================================ Version 0.3 October 25, 1997 Main changes from version 0.2 (for more information, look at the relevant sections of the greatly expanded User's Manual): - added VHDL co-simulation support (section 6.2), - added non-integer (floating point and structure) type support for software synthesis (section 5.2), - added semi-automated abstraction support for formal verification (VIS interface; section 8) - added support for CFSM execution chaining (without RTOS overhead; section 10.1) - added support for module collapsing in strl2shift (-C option; section 5.1) - removed support of e2s compiler (now you MUST use the official Esterel compiler to process Esterel input files) - removed support of golden_gate graphical CFSM editor - fully compatible with Ptolemy 0.7 - changed hierarchical pathname expansion (now the shortest unique name is used for both CFSMs and variables/signals) Main bug fixes (see the CHANGES file for more information): - fixed incorrect handling of "await tick" in Ptolemy - changed strl2shift options (-n is default, -v prints out called programs) - fixed a bug in the Ptolemy simulation that prevented some SW stars from being executed, fixed non-integer time stamp handling (from testbench) ============================================================================ Version 0.2 December 2, 1996 Main changes from version 0.1 (for more information, look at the relevant sections of the User's Manual): - restructured the processor resource library; moved modeling files from polis_lib/os to polis_lib/ptl and peripheral programming files to polis_lib/sw - replaced "is_SW" implementation attribute in ptolemy simulation with "implem" (string with values HW, SW, BEHAV) - added debugging feature to ptolemy simulation (-g option to write_pl and debug parameter of stars) - added I/O port hand-customization capability to gen_os command - added some features to ease handling of data flow components (await tick works in esterel, CFSMs can wait on a SET of events or single events) - standard Makefile in project directories now accepts "make help" Main bug fixes (see CHANGES for more details): - several problems in peripheral programming library and interrupt handling component of RTOS have been fixed - decoding at the HW side of HW/SW interface now is correct - read_library now works correctly - VHDL files generated by the blif2vst and sg_to_vhdl commands are syntactically correct ============================================================================