ERRATA to the POLIS HW/SW Codesign book

  • p. 44, 3rd paragraph "...makes it hard to specify components of a system that operate [instead of operateS] at different rates."
  • p. 54, 1. ... 2. ... matches PREVIOUS_STATE [instead of present_state] ...in order to be consistent, HOWEVER see **
  • **While it might seem better to change all occurrences of previous state to present state, that directly conflicts with the formal model described in the next section. The word previous was deliberately chosen NOT to conflict with the formal, correct description.

  • p. 84, discussion of differences between POLIS and Esterel. Note that the emit a; await a code fragment will only simulate differently in POLIS and Esterel if the feedback signal a is connected through the external asynchronous network in POLIS. For example, the POLIS system comprised of net.aux and node.strl, and the Esterel system comprised of node.strl and net.strl as follows:
  • net.aux:

    .net POLIS_NETWORK
    input i;
    output o;
    module NODE [i/i, a_in/a, a_out/a, o/o];
    .

    node.strl:

    module NODE:
    input i, a_in;
    output o, a_out;
    await i;
    emit a_out;
    await a_in;
    emit o
    end module

    net.strl:

    module ESTEREL_NETWORK:
    input i;
    output o;
    signal a in
    run NODE [signal i/i, a/a_in, a/a_out, o/o]
    end signal
    .

    would produce the behavior described in the book. See "A short note on POLIS timing semantics" for more info see A Short Note on POLIS and timing semantics .

  • 89 section 2.7.3,..."The basic statements in ESTEREL are described below and summarized in Table 2.1." (instead of Figure 2.1)
  • All "figure" should be changed to "Figure" in section 2.8 Graphical Editor (Chicago manual of style recommends lowercase for figure, section, etc, but the book is fairly consistently upper case.)
  • p. 102 "Transitions are specified in 3 steps:" (delete rest of line).
  • p. 109 footnote 6 "...with an arbitrary number of [delete second of] chidren"
  • p. 131 and also 4 occurences on p. 133 In the smoothing function, av = Szj | i <= j <= m+l , zj is an output... there should only be a strict greater than i.e. i < j <= m+l.
  • ** Of course the = case does not hurt since F cofactored w.r.t. zi does not depend on zi, but it does not add anything either, and in order to be consistent with the idea of the build procedure and the proofs,these occurences should be fixed(5 in all).

  • p. 133, bottom "...An array of pointers to...of the CFSM is associated with each output..."
  • p. 134 In order for values of the selector variable S (composed of bits Sa and Sy) 0, 1, 2 to correspond to the functionality of the Mux, Figure 3.1 should be modified to show INC_A, and RESET_A on lines 1 and 2 that correspond to output a (selected by bit Sa of the selector), and ZERO_y, ONE_y on lines 1 and 2 that correspond to output y (selected by bit Sy of the selector). With this modification the textual description and the figure would be consistent (note: the value of 0 on the selector bits represents "hold" output, select neither lines). This correction is also consistent with Figure 3.2.
  • p. 135 "The optimization of the S-GRAPH can be done directly on the BDD representing the CFSM characteristic function." (No Italics)
  • p. 136 Ordering Outputs before their Support "...The Boolean circuit is optimized using for example (instead of e.g.)..."
  • p. 142 Property 3.3.2 The form of...is determined by the type of the corresponding node
  • p. 145 section 3.3.2 "...the estimation at the S-GRAPH level...final code "structure.""
  • p. 146, top 1/4: "...The major difference is in the ordering of variables. That, in the case of the BDD used to represent the transition relation, is fixed (from the SHIFT file)."
  • p.146, top 1/3: "....The traversing algorithm for the BDD...algorithm shown above..."
  • p. 147 (& p. 148) Caption for Table 3.1 and Table 3.2 should state that named CFSMs are part of a Car Dashboard Controller Example (described in Section 7.1).
  • p. 147 (& p. 148) Caption for Table 3.1 and Table 3.2 should be below tables.
  • p. 149, top 1/4 "The CPU time required for performing the estimation is under five seconds on a DEC ..."
  • p. 149 section 3.4 Hardware Synthesis "...The hardware partition will include some (possible all) of the CFSMs in a network along with other..."
  • p. 150, bottom 1/3: "The decision...by case basis by weighing the differences in cost...."
  • p. 151 (5th bullet) "The CFSMs are composed synchronously..."
  • p. 151, last paragraph: "In terms of...the CFSM semantics are implemented...."
  • p. 151 "...the hw-CFSMs synthesized by the current version of POLIS have no input buffers..."
  • p. 152 "The result of this process can be output..."
  • p. 152 ".nb false unsigned 1 "(see **)
  • p. 153 ".nb false unsigned 1 "(see **)
  • ** All occurences of "true" and "false" can be removed from the SHIFT description without changing anything.

  • p. 154, bottom 1/3: If "false" was declared as in corrections above the we have "*c<0>...false<0> \"
  • p. 155, second to last paragraph: "Each output latch...always associated with the value 0 of the selection"
  • p. 155 Last sentence in paragraph before last can also be stated as: "Thus it is used to implement the case...no change in output."
  • p. 157 4.1 INTERFACE SYNTHESIS "2. ...and all their outputs...by the synthesis procedure described earlier."
  • p. 158 "[PORT_0E<1>] means that input event reset is assigned to bit 0 of port E....Similarly, input event key_on is assigned to bit 1 of port E....(see **)
  • ** i.e. PORT_**<m> corresponds to bit log_2(m)

  • p. 160 "Figure 4.2 The hardware/software interface for the EISA bus"
  • p. 160 4.2 REAL-TIME OPERATING SYSTEM SYNTHESIS "...and to ensure that they, together with...(mp-CFSMs, see section 4.3.5), implement a valid ..."
  • p. 161, top "...schedule sw-CFSMs such that..."
  • p. 166 section 4.3.3 "...thus generating a pulse which is then sensed by the..."
  • p. 169, end of first paragraph: "...tasks with very different cost-performance trade-offs."
  • p. 169 paragraph before last: "Othewise, if it is assigned to the hardware partition...are applied to the library model." Actually, it is unclear what the author of this piece of text intended. Perhaps it is true that the simulation model from Ptolemy is used. This needs to be clarified.
  • p. 170 section 4.3.6 1st bullet: "...on whether the macro e_T_polled is defined..."
  • p. 171 section 4.3.7 first paragraph: "...and making sure protocols for event passing are followed."
  • p. 172 section 4.4 "...These are the only microcontroller resources that the RTOS deals with explicitly."
  • p. 173 4th bullet 2nd paragraph: "This mechanism currently does not permit the specification of a programmable I/O port"
  • p. 173 1st bullet says that memory-size & hwsw-sec-size are decimal numbers while Figure 4.6 shows hex numbers. These numbers are not used currently so it makes no difference.
  • p. 180, last paragraph...(i.e. such a file must exist in some of the... "
  • p. 182, first line"...level of detail that we have used..."
  • p. 183 footnote 4 "...that helps in determining an..."
  • p. 184, second sentence of large paragraph "...However, pre-runtime scheduling requires executing a task..."
  • p. 188 3rd criteria "If some task...In other words,...,we cannot make it pass by lowering its priority."
  • p. 191 section 4.7 "...(in the case of POLIS, a network of CFSMs)."
  • p. 192 4th paragraph: "The concept of WCET...as well as for preemptive and non-preemptive schema."
  • p. 193 2nd paragraph: Assume that we want to compute the WCET of the task with the lowest..."
  • p. 193 4th paragraph "...If...is shorter than the period of the task with priority p then the WCET..."
  • p. 195 5th bullet "...such that the total amount...in which i has the highest priority among enabled tasks (i.e. the total run time)..."
  • p. 197 last paragraph, point 1 "In the worst case, at the very beginning of..."
  • p. 201 1st paragraph "...that the physical characteristics of a prototype are generally comparable to those of the final implementation. "
  • p. 201 3rd paragraph, better stated as: "...It can dramatically improve the performance/cost ratio for a product..." since readers may associate improve with increase.
  • p. 203 Figure 5.1 bottom Physical Prototype on APTIX FBCB should read "Emulator Pod" instead of "Pod Emulator".
  • p. 207 2nd paragraph, top 1/4 "...where events are ordered based on their time-stamps; at any given..."
  • p. 208 point 1 "...The C code also includes run time estimates for each..."
  • p. 208 point 5, 1st bullet "an implementation, either software or hardware, and"
  • p. 210 1st bullet, 3rd subpoint: "if the current time identifies an update phase..."
  • p. 212 point 2 "...This information permits the identification of critical components..."
  • p. 212 point 3 "...task scheduling charts, including..."
  • p. 212 "All this information can greatly help in deriving the correct selection of an..."
  • p. 212 last paragraph "Using the PTOLEMY graphical interface makes these tasks easy and..."
  • p. 213 last paragraph of section 5.3.2 "All the signals... debug code (see section 5.3.4 on the commands)."
  • p. 213 last paragraph of section 5.3.2: "...for later inspection, for example, with some graphical analysis program."
  • p. 213 "Execution speed: the simulation is fast..." **
  • p. 213 "Interactivity: the user can change..." **
  • **Actually, these paragraphs should be reformatted. There should not be two semi-colons as suggested by the corrections above, yet, the current formatting is awkward as well.

  • p. 214 2nd paragraph "The accuracy of this method of performing co-simulation...precision of the running time estimates of the generated code."
  • p. 218 footnote 2 "Without creating...which would require deleting it afterwards to..."
  • p. 219 last sentence of paragraph that starts with "No parameters.. .": "On the other hand,..."
  • p. 220 1st paragraph "They are particularly...because they permit the display of several signals..."
  • p. 222 "Using the POLIS palette...that help in designing a system..."
  • p. 223 1st paragraph "...that support it (typing the command ...instance shows which implementations..."
  • p. 223, same place: "Even if the designer is not planning..."
  • p. 228 point 1, first paragraph after (b) "...to specify an individual CFSM."
  • p. 229 3rd bullet "A gate level...component declarations and instantiations:"
  • p. 230 1st paragraph and what follows should be under a new subsection 5.5.2 Behavioral VHDL generation
  • p. 232: for the text, the font is too small. It matches the font size of the example, not of normal text.
  • p. 233 1st paragraph "...thus retaining the possibility of changing the implementation..."
  • p. 235 last paragraph "...unbounded amount of time. This assumption ..."
  • p. 236 section 5.6.1 Verification Methodology "...a set of automata that together represent the behavior."
  • p. 239 1st paragraph "Verification will be accomplished by the use of fairness constraints."
  • p. 243 bottom of page: "P1.1': If four..."
  • p. 247 1st paragraph "This is usually...components are used , or when company policy..."
  • p. 249 last paragraph "Simulating external...does not require rewriting its specification..."
  • p. 250 2nd paragraph "Unfortunately, POLIS cannot help... using other automated tools(for example [48])."
  • p. 251 The following line of code should be as follows: "status=cxewatm(RESET|KEY_ON|KEY_OFF|BELT_ON|OC_END,0,2);". Mode 2 in CMX means clear events after there is a match.
  • p. 252 "/* Terminate task*/; cxtend();" is not really needed since the task is never going to hit the end brace because of the while(1) loop.
  • p. 255 Chapter 7 All occurences of "figure" in the text should be replaced with "Figure"
  • p. 256 last paragraph "r.p.m., and the kilometers travelled:..."
  • p. 257 Figure 7.2 should read "The wheel motion sensor as input to the dashboard"
  • p. 265(& p. 266) The caption in Table 7.1 and Table 7.2 should state that the CFSMs listed are from the PROSA design example (described in Section 7.2.1)
  • p. 267 section 7.2.3 Hardware synthesis "We are currently in the process of validating this data experimentally."
  • p. 267 section 7.3 2nd paragraph "The system...to the actual load that appears on the wheels,..."
  • p. 271 1st paragraph "46639 bytes of ROM and 10229 bytes of RAM..."
  • Appendix A (GLOSSARY) p. 276 captured input assignment: the input assignment a CFSM reads for a particular execution.
  • Appendix B (THE SYNTAX OF SHIFT), p. 281 first paragraph: "...In the following, a keyword is denoted by the courier font" write the words "courier font" IN Courier font.
  • Index p. 289 sub-networks, 36 sub-network instantiation, 36
  • References p. 294 reference [39] "...third edition version 3.10."


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Last Updated January 8, 1998
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