The MVSIS group at Berkeley studies logic synthesis and verification for VLSI design. The main focus is on new optimization algorithms that improve the quality of circuits generated by automatic synthesis tools and, at the same time, are scalable for practical use.


Most of the algorithms developed by our group are incorporated in an open-source program called MVSIS which is the successor of the SIS program, also developed here at Berkeley. Although the initial focus of MVSIS was on logic minimization for multivalued networks, over time it has developed into a full featured tool for synthesis and verification in general.

research areas

Currently we focus on five main areas of research.

Multi-Valued Logic Synthesis
Generalization of classical binary logic minimization to general multi-valued networks.
Boolean Technology Mapping
Using locally boolean matching techniques, resynthesis and area minimization to improve runtime and quality of FPGA and standard cell mapping.
Language Equation Solving
Practical aspects of using language equation solving for sequential synthesis.
Combinational Verification
Using techniques from combinational verification to improve logic synthesis.
Physically-Aware Synthesis
Incorporating physical design issues such as wire-length and congestion in synthesis.

this website

You can get more information about each of these areas by following the links to the left. You can also download the latest binary and source releases of MVSIS, as well as related technical reports and published papers.

the software

In addition to algorithms for multi-valued logic, MVSIS includes fast binary synthesis algorithms, technology mapping and resynthesis procedures and state-of-the-art engines for combinational and sequential equivalence checking. There are stand-alone binaries for Windows and Linux that you can download from the link on the left.

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