VERILOG description

VERILOG description

Module main(clk);

input clk, reqA, reqB, reqC;

output ackA, ackB, ackC;

selection wire sel;

wire active;

assign active = pass_tokenA || pass_tokenB || pass_tokenC;

controller controllerA(clk, reqA, ackA, sel, pass_tokenA, A);

controller controllerB(clk, reqB, ackB, sel, pass_tokenB, B);

controller controllerC(clk, reqC, ackC, sel, pass_tokenC, C);

arbiter arbiter(clk, sel, active);

endmodule

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