The VIS group would be happy to help with your verification problems.
Our research is always helped by exposure to industrial problems, and
we welcome it. If you need help with formal verification,
VIS can provide help in one of the following ways.
You could send mail to the VIS group with a description of your
problem. If it is a bug, we would send you a patch. If it is a
question, we would be happy to answer it.
You can send us an example if you want help trying to verify it.
We would be willing to put in some effort into trying to figure
out ways to verify it. If you observe a problem
with VIS on your example, we encourage you to create a "small"
example that can reproduce the problem and send the "small" example
to us. We will make every effort to fix the problem or offer assistance in
creating a work-around for you. If you send us an example, we will be
bound by non-disclosure.
If you need more help in setting up VIS, or verification help that is
more closely tied with your design process, some of us may be able to
visit you and help you sort out your verification cum VIS problems.
As before, we will be bound by non-disclosure.
Caveat: This is an educational exercise, hence there are no guarantees.