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Introduction
People Research
themes: Embedded Systems
Hybrid Systems
Deep Submicron
Logic Synthesis
Other links:
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GSRC
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Logic Synthesis
Publications:
S.
Khatri, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Cross-talk Immune VLSI Design Using Regular
Layout Fabrics. Kluwer Academic Publishers, 2001.
M.
D. Di Benedetto, A.
L. Sangiovanni-Vincentelli, and T.
Villa. Model Matching for Finite State Machines. IEEE Transactions on
Automatic Control, 46(11):1726-1743, November 2001.
N.
Yevtushenko, T.
Villa, R.
K. Brayton, A.
Petrenko, and A.
L. Sangiovanni-Vincentelli. Solution of Parallel Language Equations for
Logic Synthesis. In The Proceedings of the International Conference on
Computer -Aided Design, pages 103-110, November 2001.
L.
Lavagno, T.
Villa, and A.
L. Sangiovanni-Vincentelli. Advances in Encoding for Logic Synthesis. In G.
W. Zobrist, editor, VLSI Design Environments. Gordon and Breach Science
Publishers, 2000.
A.
Aziz, F.
Balarin, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Sequential synthesis using S1S. IEEE
Transactions on Computer-Aided Design, 19(10):1149-1162, October 2000.
E.I. Goldberg, L.P. Carloni, T. Villa, R. K. Brayton and
A.L. Sangiovanni-Vincentelli, Negative Thinking in Branch-and-Bound: the Case of Unate
Covering,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 3, March 2000.
L.P. Carloni, E.I. Goldberg, T. Villa, R.K. Brayton and
A.L. Sangiovanni-Vincentelli, Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering
Problems,
In "VLSI: Systems on a Chip" (L.M. Silveira, R. Reis, S. Devadas editors), Kluwer 1999.
A.L. Oliveira,
L.P. Carloni, T. Villa and A.L. Sangiovanni-Vincentelli, Exact
Minimization of Binary Decision Diagrams Using Implicit Techniques, IEEE
Transactions on Computers, Vol. 47, No. 11, November 1998.
E.
Goldberg, T.
Villa, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Theory and Algorithms for Face Hypercube
Embedding. IEEE Transactions on Computer-Aided Design, 17(6):472-488,
June 1998.
T.
Kam, T.
Villa, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Multi-Valued Decision Diagrams: Theory and
Applications. International Journal on Multiple-Valued Logic,
4(1-2):9-62, 1998.
W.
Gosti, T.
Villa, A.
Saldanha, and A.
L. Sangiovanni-Vincentelli. An Exact Input Encoding Algorithm for BDDs
Representing FSMs. In Proceedings of the 8th Great Lakes Symposium on VLSI,
pages 294-300, February 1998.
A.L. Oliveira, L.P.
Carloni, T. Villa and A.L. Sangiovanni-Vincentelli,
Exact Minimization of Binary Decision Diagrams Using Implicit Techniques,
IEEE Transactions on Computers, Vol. 47, No. 11, November 1998.
T.
Kam, T.
Villa, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Synthesis of FSMs: Functional Optimization.
Kluwer Academic Publishers, 1997.
T.
Villa, T.
Kam, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Synthesis of FSMs: Logic Optimization. Kluwer
Academic Publishers, 1997.
T. Kam, T.
Villa, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Implicit Computation of Compatible Sets for
State Minimization of ISFSMs. IEEE Transactions on Computer-Aided Design,
16(7):657-676, July 1997.
T.
Kam, T.
Villa, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Theory and Algorithms for State Minimization of
Nondeterministic FSMs. IEEE Transactions on Computer-Aided Design,
16(11):1311-1322, November 1997.
T.
Villa, T.
Kam, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Explicit and Implicit Algorithms for Binate
Covering Problems. IEEE Transactions on Computer-Aided Design,
16(7):677-691, July 1997.
T.
Villa, A.
Saldanha, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Symbolic Two-Level Minimization. IEEE
Transactions on Computer-Aided Design, 16(7):692-708, July 1997.
P. Buch, A.
Narayan, R.
Newton, and A.
L. Sangiovanni-Vincentelli. Logic Synthesis for Large Pass Transistor
Circuits. In The Proceedings of the International Conference on
Computer-Aided Design, pages 663-670, November 1997.
L.
P. Carloni, P.
McGeer, A.
Saldanha, and A.
L. Sangiovanni-Vincentelli. Trace-Driven Logic Synthesis: Application to
Power Minimization. In The Proceedings of the International Conference on
Computer-Aided Design, pages 581-588, November 1997.
A.
L. Oliveira, L. P. Carloni, T.
Villa, and A.
L. Sangiovanni-Vincentelli. An Implicit Formulation for Exact BDD
Minimization of Incompletely Specified Functions. In Ricardo Reis and Luc
Claesen, editors, VLSI: Integrated Systems on Silicon, Proceedings of VLSI
'97, Gramado, Brazil, pages 315--326, August 1997. Chapman-Hall.
E.I. Goldberg, L.P. Carloni, T. Villa, R.K. Brayton and
A.L. Sangiovanni-Vincentelli, Negative Thinking in Search Methods: Application to Unate
Covering,
The Proceedings of the International Conference on Computer-Aided Design, 1997.
W.
Lam, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Valid Clock Frequencies and Their Computation in
Wavepipelined Circuits. IEEE Transactions on Computer-Aided Design,
15(7):791-807, July 1996.
A.
L. Oliveira and A.
L. Sangiovanni-Vincentelli. Using the Minimum Description Length Principle
to Infer Reduced Ordered Decision Graphs. Machine Learning, 25(1):23--50,
October 1996. Kluwer Academic Publishers.
P.
Stephan, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Combinational Test Generation Using
Satisfiability. IEEE Transactions on Computer-Aided Design,
15(9):1167-1176, September 1996.
R.
K. Brayton, G.
Hachtel, A.
L. Sangiovanni-Vincentelli, F.
Somenzi, A.
Aziz, S.-T.
Cheng, S.
Edwards, S.
Khatri, Y.
Kukimoto, A.
Pardo, S.
Qadeer, R.
Ranjan, S.
Sarwary, T.
Shiple, G.
Swamy, and T.
Villa. VIS: A System for Verification and Synthesis. In R. Alur and T.
Henzinger, editors, The Proceedings of the Conf. on Computer-Aided
Verification, volume 1102 of LNCS, pages 332-334, August 1996.
Springer Verlag.
R.
K. Brayton, G.
Hachtel, A.
L. Sangiovanni-Vincentelli, F.
Somenzi, A.
Aziz, S.-T.
Cheng, S.
Edwards, S.
Khatri, Y.
Kukimoto, A.
Pardo, S.
Qadeer, R.
Ranjan, S.
Sarwary, T.
Shiple, G.
Swamy, and T.
Villa. VIS. In M. Srivas and A. Camilleri, editors, Proc. of the Conf.
on Formal Methods in Computer-Aided Design, volume 1166 of LNCS,
pages 248-256, November 1996. Springer Verlag.
T.
Shiple, V.
Singhal, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Analysis of Combinational Cycles in Sequential
Circuits. In The Proceedings of the International Symposium on Circuits and
Systems, pages 592-595, vol. IV, May 1996.
R.
Murgai, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Logic Synthesis for Field-Programmable Gate
Arrays. Kluwer Academic Publishers, 1995.
W.
Lam, A.
Saldanha, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Delay Fault Coverage, Test Set Size, and
Performance Tradeoffs. IEEE Transactions on Computer-Aided Design,
14(1):32-44, January 1995.
P.C.
McGeer, K.L.
McMillan, A.
Saldanha, A.
L. Sangiovanni-Vincentelli, and P.
Scaglia. Fast discrete function evaluation using decision diagrams. In The
Proceedings of the International Conference on Computer-Aided Design, pages
402-407, November 1995.
A.
Saldanha, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Circuit Structure Relations to Redundancy and
Delay. IEEE Transactions on Computer-Aided Design, 13(7):875-883, July
1994.
A.
Saldanha, T.
Villa, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Satisfaction of Input and Output Encoding
Constraints. IEEE Transactions on Computer-Aided Design, 13(5):589-602,
May 1994.
A.
Malik, R.
K. Brayton, R.
Newton, and A.
L. Sangiovanni-Vincentelli. Two-Level Minimization of Multivalued Functions
with Large Offsets. IEEE Transactions on Computer-Aided Design,
42(11):1325-1342, November 1993.
S.
Malik, K.
J. Singh, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Performance Optimization of Pipelined Logic
Circuits Using Peripheral Retiming and Resynthesis. IEEE Transactions on
Computer-Aided Design, 12(5):568-578, May 1993.
P.
McGeer, J.
Sanghavi, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. ESPRESSO-SIGNATURE: a New Exact Minimizer for
Logic Functions. IEEE Transactions on VLSI Systems, 1(4):432-440,
December 1993.
A.
L. Oliveira and A. L. Sangiovanni-Vincentelli. Learning Complex Boolean Functions : Algorithms
and Applications. In Advances in Neural Information Processing Systems 6,
Denver, CO, pages 911--918, 1993. Morgan Kaufmann.
N.
Shenoy, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Resynthesis of Multi-Phase Pipelines. In The
Proceedings of the 30th ACM/IEEE Design Automation Conference, pages
490-496, June 1993.
P.
McGeer, A.
Saldanha, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Delay Models and Exact Timing Analysis. In T.
Sasao, editor, New Trends in Logic Synthesis and Optimization. Kluwer,
1992.
S.
Malik, L.
Lavagno, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Symbolic Minimization of Multilevel Logic and
the Input Encoding Problem. IEEE Transactions on Computer-Aided Design,
11(7):825-843, July 1992.
A.
L. Oliveira and A.
L. Sangiovanni-Vincentelli. Constructive Induction Using a Non-Greedy
Strategy for Feature Selection. In Proceedings of the Ninth
International
Conference in Machine Learning, Aberdeen, Scotland, pages 355--360, 1992.
Morgan Kaufmann.
N.
Shenoy, K.
J. Singh, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. On the Temporal Equivalence of Sequential
Circuits. In The Proceedings of the 29th ACM/IEEE Design Automation
Conference, pages 405-409, June 1992.
A.
Malik, R.
K. Brayton, R.
Newton, and A.
L. Sangiovanni-Vincentelli. Reduced Offsets for Minimization of
Binary-Valued Functions. 10(4):413-426, April 1991.
S.
Malik, E.
M. Sentovich, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Retiming and Resynthesis: Optimizing Sequential
Circuits Using Combinational Techniques. 10(1):74-84, January 1991.
A.
L. Oliveira and A.
L. Sangiovanni-Vincentelli. Learning Concepts by Synthesizing Minimal
Threshold Gate Networks. In L. Birnbaum and G. C. Collins, editors, Proceedings
of the Eigth International Workshop in Machine Learning, Chicago, IL, pages
193--197, 1991. Morgan Kaufmann.
A.
L. Oliveira and A.
L. Sangiovanni-Vincentelli. LSAT - An Algorithm for the Synthesis of Two
Level Threshold Gate Networks. In The Proceedings of the International
Conference on Computer-Aided Design, Santa Clara, CA, pages 130--133, 1991.
IEEE Computer Society Press.
N.
Shenoy, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Retiming of Circuits with Single Phase
Transparent Latches. In The Proceedings of the International Conference on
Computer Design, pages 86-89, October 1991.
R. K. Brayton, A.
L. Sangiovanni-Vincentelli, and G. Hachtel. Multi-level logic synthesis. Proceedings
of the IEEE, vol. 78(no. 2):264-300, February 1990.
T.
Villa and A.
L. Sangiovanni-Vincentelli. NOVA: State Assignment for Optimal Two-Level
Logic Implementations. IEEE Transactions on Computer-Aided Design,
9(9):905-924, September 1990.
S.
Devadas, A.
Wang, R.
Newton, and A.
L. Sangiovanni-Vincentelli. Boolean Decomposition in Multilevel Logic
Optimization. IEEE Journal of solid-state circuits, pp 399-408, April
1989.
K.
Bartlett, R.
K. Brayton, G. Hachtel, R.
Jacoby, C.
Morrison, R.
Rudell, A.
L. Sangiovanni-Vincentelli, and A.
Wang. Multi-level Logic Minimization using Implicit Don't Cares. transcad,
June 1988.
R.
K. Brayton, R.
Rudell, A.
L. Sangiovanni-Vincentelli, and A.
Wang. MIS: A Multiple-Level Logic Optimization System. IEEE Transactions
on Computer-Aided Design, pp 1062-1081, November 1987.
R.
Rudell and A.
L. Sangiovanni-Vincentelli. Multiple-Valued Minimization for PLA
Optimization. IEEE Transactions on Computer-Aided Design, CAD-6:727-750,
September 1987.
G.
De Micheli, R.
K. Brayton, and A.
L. Sangiovanni-Vincentelli. Optimal State Assignment for Finite State
Machines. IEEE Transactions on Computer-Aided Design, CAD-4:269-285, July
1985.
R.
K. Brayton, G.
Hachtel, C.
McMullen, and A.
L. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI
Synthesis. Kluwer Academic Publishers, 1984.
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