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TraceDriven Logic Synthesis
A trace driven methodology for logic synthesis and optimization is proposed.
Given a logic description of a digital circuit C and an expected trace
of input vectors T, an implementation of C that optimizes a
cost function under application of T is derived.
This approach is effective in capturing and utilizing the correlations that
exist between input signals on an application specific design.
The idea is novel since it propose synthesis and
optimization at the logic level where the goal is to optimize the
average case rather than the worst case for a chosen cost metric.
This paper focuses on the development of algorithms for trace driven
optimization to minimize the switching power in multilevel networks.
The average net power reduction (internal plus I/O power) obtained on a set of
benchmark FSMs is 14%, while the average reduction in internal power is
25%. We also demonstrate that the I/O transition activity provides an upper
bound on the power reduction that can be achieved by combinational logic
synthesis.
Publications:
L.P. Carloni, P. McGeer, A. Saldanha and
A.L. SangiovanniVincentelli,
TraceDriven Logic Synthesis: Application to Power Minimization,
The Proceedings of the International Conference on ComputerAided Design, 1997.
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