EECS 144/244

Fall 2015

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EECS 144/244 Lectures Fall 2013

(click on title for slides in PDF)
No. Date Topic Reading Milestones
1a 8/29 Introduction, Logistics [SAS+ST] Special issue of IEEE Solid-State Circuits Magazine  
1D 8/30 Perl Tutorial (video - contact TAs for username/password)    
2a 9/3 Design Methodologies: Model-Based Design, RTL Flow [ST+SAS].    
2b 9/5 Timing Analysis - 1 [SAS] In-class handout (also posted on bSpace):Chapter 5 of Timing" by S. Sapatnekar
Optional: Chapter 15 of Lee and Seshia
 
2D 9/6 Timing Analysis - Discussion on Algorithms & Complexity [SAS] Appendix B of Lee and Seshia  
3a 9/10 Timing Analysis - 2 [SAS] Floating-Mode Delay paper, Devadas et al.  
3b 9/12 Retiming [SAS] Shenoy, N, "Retiming: Theory and Practice" HW 1 out
3D 9/13 Software Engineering Best Practices 1 [] Resources  
4a 9/17 Basic Boolean algebra and logic optimization [SAS]    
4b 9/19 Boolean algebra and logic optimization (contd.) [SAS] Multi-level logic synthesis paper (Sections I-IV, topics mentioned in the slides)  
4D 9/20 Software Engineering Best Practices 2 []    
5a 9/24 Binary Decision Diagrams (BDDs) [SAS] ACM Computing Surveys paper: Required reading; Knuth's chapter: optional reading  
5b 9/26 Boolean satisfiability (SAT) solving [SAS]
Other slides: DLL-Example-1, DLL-Example-2, BCP Introduction, BCP 2-literal watching.
CACM Article on SAT  
5D 9/27 Observability and controllability (stuck-at testing) [SAS] Goel '81; Larrabee '92  
6a 10/1 Reachability analysis (sequential equivalence checking) [SAS] Ch. 14 of Lee & Seshia HW 1 due, HW 2 out
6b 10/3 Temporal Logic, start Model Checking [SAS] Ch. 12 of Lee & Seshia  
6D 10/4 Model Checking [SAS] Clarke, Grumberg, Long paper  
7a 10/8 Synchronous Systems [ST] Chapter "Synchronous-Reactive Models" of Ptolemy book, Malik, Cyclic Combinational Circuits, 1994 Project proposals due
7b 10/10 Synchronous Systems: Symbolic Execution [ST] Edwards and Lee, Synchronous, 2003, Shiple Et. Al, CyclicCircuits, 1996, Edward A. Lee (2011), Concurrent Models of Computation: An Actor-Oriented Approach, Chapter 1: Partially Ordered Sets. HW 2 due, HW 3 out
7D 10/11 Discussion: Compositionality in Synchronous Systems[ST] Lublinerman et al. (POPL'09), Modular Code Generation from Synchronous Block Diagrams  
8a 10/15 Scheduling algorithms in dataflow [ST] Lee & Messerschmitt, SDF, Lee & Messerschmitt, Static Scheduling, Kahn 1974  
8b 10/17 Project mini-updates    
8D 10/18 Midterm 1 review [MZ]   HW 3 due (Oct. 20)
9a 10/22 Throughput analysis in timed dataflow [ST] Ghamarian et al 1996  
9b 10/24 Midterm 1 (in class)   HW 4 out
9D 10/25 Midterm 1 solutions    
10a 10/29 Discrete-event simulation [ST] Lee 1999, Misra 1986  
10b 10/31 Timed automata [ST] Alur Dill 1994  
10D 11/1 SystemC, Verilog, VHDL overview [MZ]    
11a 11/5 Continuous and hybrid systems - part 1 [ST] Chapter 2 of Continuous Simulation by F. Cellier
11b 11/7 Continuous and hybrid systems - part 2 [ST]   HW 4 due
11D 11/8 Signal Temporal Logic, Breach [Alex Donze] Tools: Breach (ODE simulation, STL) HW 5 out
12a 11/12 DAEs, Modelica [DB]  
12b 11/14 DAEs, Modelica [DB]  
12D 11/15 Spin tutorial [MZ]    
13a 11/19 Controller synthesis [ST] Pnueli-Rosner POPL'89, Ehlers PhD Chapter 4  
13b 11/21 Program synthesis [ST] Alur et al, FMCAD 2013, Solar-Lezama STTT 2013  
13D 11/22 Synthesis tools [Christos Stergiou]   HW 5 due, HW 6 out
14a 11/26 Stochastic systems: Markov Chains and Markov Decision Processes [ST] Chapter 10 of Principles of Model Checking, by Baier, Katoen  
14b 11/28 Thanksgiving recess, no class    
14D 11/29 Thanksgiving recess, no discussion section    
15a 12/3 Midterm 2 review [ST]    
15b 12/5 Midterm 2 (in class)    
15D 12/6 Wrap-up; Midterm2 solutions   HW 6 due
  12/10 NO CLASS: RRR week.    
  12/12 Project presentations, 1-6pm, 540 Cory    

 
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