Systems Design Seminar
A C-Based Parallelizing
Growing size and
complexity of microelectronic systems calls for design modeling, synthesis
and validation techniques at higher levels of abstraction. In this talk,
I will present our approach to the
automated synthesis and optimization of digital circuits from behavioral descriptions.
While such "high-level" synthesis approaches have been explored for years,
what sets our work apart are the aggressive
code parallelizing and code motion techniques that significantly improve the
quality and controllability of the synthesis results. Specifically, I will
focus on speculative code motion and innovative dynamic complier
optimization techniques and their effect on design quality in terms of
cycle time, circuit size and interconnect/control
costs. These techniques have been implemented in a synthesis framework called
SPARK. I will describe the architecture of SPARK and experimental
results on a number of benchmarks and an example case study of the
Instruction Length Decoder block from the Intel Pentium processor that
demonstrates the utility of our approach.
Publications and binaries for SPARK can be downloaded from: http://www.cecs.uci.edu/~spark
Sumit Gupta received his Ph.D. from the University of California, Irvine in June 2003 and his B.Tech from IIT Delhi in 1995. He is currently a Post-Doctoral researcher with Professors Rajesh Gupta and Nikil Dutt at UC San Diego and Irvine. His research interests lie in the Codesign and synthesis of the Hardware and Software of Embedded Systems, Reconfigurable Computing, Low Power techniques for Mobile Devices and Parallelizing Compiler Techniques.