Pre-requisites: If you need cross-platform compatibility (I am using Redhat Linux with g++ on x86), please use the following version of autoconf: 2.5.7 automake: 1.6.3 g++: 3.2.2-5 recommended C++ flags for speed: -O3 -fomit-frame-pointer -finline-limit-1500 Note: You may also need python (v. 2.2.2) to install the package, but it is not necessary if you can manually install the package by inspecting the installing python script. ------------------------------------------------ -------------------------------------------------- Installing: 1. unzip and untar the cc_bus_rel_0.1.tar.gz in an empty directory 2. change directory to INSTALL_DIR/coreconnect_rel 3. type ./goInstall to install the software. It should take about less than 5 minutes on a fast x86 machine (such as P4) ------------------------------------------------------ ------------------------------------------------------ Quick Run of a bus operation example with CoreConnect Bus Functional Language (BFL) --------------------------------------------------------- ------------------------------------------------------- 1. change directory to INSTALL_DIR/coreconnect_rel/mad2/sample/ns 2. run cp test/506/*.bfl . it should copy 8 bfl files contained in the test bench directory corresponding to figure 13 in the coreconnect 32-bit PLB architecture specification (a.k.a Doc 1). These 8 bfl files are for the scenario that 4 master connected to 4 slaves by a coreconnect bus. 3. run ./ns_test This step run the simulator. It should produce the following result at the end. Primary read: 3, 0 at time = (1.0) Primary write: 3, 0 at time = (2.0) Begin Primary write: 3, 0 at time = (2.1) End Primary write: 3, 0 at time = (2.2) Secondary read: 3, 0 at time = (3.0) Begin Primary read: 3, 0 at time = (3.1) End Primary read: 3, 0 at time = (3.2) Primary write: 3, 0 at time = (4.0) Begin Primary write: 3, 0 at time = (4.1) End Primary write: 3, 0 at time = (4.2) Begin Secondary read: 3, 0 at time = (5.1) End Secondary read: 3, 0 at time = (5.2) 16 12 8 0.000000 Total user time : 3.340 sec. Total system time: 0.000 sec. Total cycles: 1000001 cyc. Simulation speed : 2.994e+05 cyc./sec. Interpretation of Simulation Output: In the current release the output format is still primitive. Every change of the operation status is marked by a single output line. For example, in the above example, Primary write: 3, 0 at time = (2.0) Begin Primary write: 3, 0 at time = (2.1) End Primary write: 3, 0 at time = (2.2) It means the write operation is asserted as a request to the bus at cycle 2, phase 0 - which is the meaning of denotation of (2,0)- and it is on the write data bus at cycle 2, phase 1 (note. every transfer happens at the transfer phase, which is the phase 1 of the cycle). Finally the operation ends with the deassertion of the write data bus at cycle 2, phase 2 (i.e. the acknowledge phase of the cycle). The above example demonstrates read/write operation in an address-pipeline enable configuration, which is the default configuration for this release. So the operation could be either the "primary" operation or the "secondary" operation depending on the precedence of the operations. ---------------------------------------------------------------------- ---------------------------------------------------------------------- More In-Depth Hacking of the System ---------------------------------------------------------------------- This package contains 25 test cases for the CoreConnect bus. These test cases roughly correspond to the waveform diagrams listed in Doc. 1. There is one waveform in Doc.1 which is not modeled. It is in Section 5.1.21, Bus Time-Out Transfer. For Section 5.1.20, we take liberty in interpreting that the write operation is only gated as the main data write operation after cycle 4. Other than these caveats, all other waveforms are faithfully represented. Note that since Doc. 1 states that "the signal assertion and negation times as shown in these diagrams, are only meant to illustrate the dependency on the rising edge of SYS_plbClk and in no way are they intended to show real timing signal timing", we only model these diagrams to show the capability of our tools and in no way mean to guarantee our model correspond to real signal timings. ---------------------------------------------------------------------- For Advanced Designers ---------------------------------------------------------------------- More advanced designers may wish to get hands on the description synthesis tools. Here is how: 1. change directory to INSTALL_DIR/core_connect_rel/mad2/sample/ns "ns_cc_bus_response.mad" is the input to the simulator synthesis tools. It is written in MADL. For further information on MADL, please refer to Mescal Architecture Description Language 1.0, Draft, By Wei Qin. ------------------------------------------------------ ------------------------------------------------------ ALL THE SOFTWARE ON THIS SITE IS RELEASED "AS IS." THE AUTHORS MAKE NO WARRANTIES, EITHER EXPRESS OR IMPLIED, REGARDING THE USE OF THIS SOFTWARE FOR ANY PARTICULAR PURPOSE.