Multiprocessor Architecture Watch
Concurrency Abstraction Watch

Processing Element Architecture View

In a traditional hardware description language (HDL), a processor is described at the bit-level, with little formal distinction between the control logic and the datapath. The desired instruction set must somehow be externally verified against this description of the processor. In contrast, the Tipi framework describes a processor as a graph of primitive computational components (termed actors) and rules about when and in what ways each actor can be used. The actors communicate via signals that are colored by the values and types of data that they carry. For instance, a simple binary adder might specify that it can be properly used only if both of its input signals are colored as valid integers. In this case, its output is now constrained to be a valid integer as well. An actor may have multiple valid ways in which it can be used. A common case is that an actor, in addition to its "normal" behavior, may sometimes do nothing. In the example of the simple adder, this would mean that another valid use of the adder would be the case where both the inputs and the output are colored as carrying no data. This constrains the possible uses of the processor as a whole to those configurations that perform useful computation. The problem of determining the set of operations that the processor can perform becomes the process of enumerating all possible combinations of the ways the actors can be used. The resulting combinations, called operations, make up the instruction set of the processor.

In the Architecture View shown below, designers connect micro-architecture actors in a schematic editor to create the architecture. A theorem prover is then used to extract the state-to-state operations supported by the architecture.

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