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Yujia Jin

Bio:

Yujia Jin received his B.S. degree in EECS at U.C. Berkeley in 1999. He is currently a Ph.D. student in the EE department at U.C. Berkeley. His research interests include memory architecture, design space exploration, and soft core multiprocessor system on FPGA.

Abstract:

Design space exploration in memory architecture can be extremely challenging due to the expanding design space, increasing architectural heterogeneity, performance evaluation complication, and shorter design cycle that the designer must face. Consequently, the designers are frequently forced to explore only a small section of all the possibilities in detail and the final chosen design can often be far from optimal. In our approach to this problem, we use a multi-tiered exploration system. At each tier, we prune the design space with an evaluation method. The top designs within the estimated margin of error are maintained for further pruning in the next tier. As we progress from one tier to the next, we use progressively more accurate but slower evaluation methods. The multi-tiered exploration system resembles a form of branch and bound exploration. It allows the designer to spend most of the design time analyzing the most interesting designs. Currently, we are applying our exploration system on network applications implemented on top of FPGA-based soft multiprocessor systems. Two tiers of pruning stage are used after the initial design space pruning by the designer. The initial tier leverages ILP formulation for evaluation. The second tier uses direct implementation. Initial result shows tens of thousands of designs can be evaluated within days versus weeks or months if done by hand.

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