Multi-Valued Logic Synthesis
Boolean Technology Mapping
Berkeley Language and Automata Manipulation
People / Contact
The MVSIS group at Berkeley studies logic synthesis and verification for VLSI design. The main focus is on new optimization algorithms that improve the quality of circuits generated by automatic synthesis tools and, at the same time, are scalable for practical use.
Most of the algorithms developed by our group are incorporated in an open-source program called MVSIS which is the successor of the SIS program, also developed here at Berkeley. Although the initial focus of MVSIS was on logic minimization for multivalued networks, over time it has developed into a full featured tool for synthesis and verification in general.
Currently we focus on five main areas of research.
You can get more information about each of these areas by following the links
to the left. You can also download
the latest binary and source releases of
MVSIS, as well as related technical reports and published papers.
In addition to algorithms for multi-valued logic, MVSIS includes fast binary synthesis algorithms, technology mapping and resynthesis procedures and state-of-the-art engines for combinational and sequential equivalence checking. See the Download Software page for source code, documentation and Linux and Windows binaries.