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Multi-Valued Logic Synthesis

Boolean Technology Mapping

Berkeley Language and Automata Manipulation

Combinational Verification

Physically-Aware Synthesis

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motivation

Multi-level multi-valued (MV) logic synthesis can have many applications including:

  • Logic synthesis for multi-valued hardware devices such as current-mode circuits.
  • Initial manipulation of a hardware description before it is encoded into binary and processed by standard binary logic synthesis programs; MV is a natural way to describe procedures at a higher level.
  • A front end to a software compiler for embedded control applications. Software lends itself naturally to the evaluation of multi-valued variables in a single cycle. For embedded applications specified from synchronous languages with finite state machine semantics, strong logic synthesis transformations can be applied for control flow optimization.
  • Asynchronous synthesis of delay insensitive (DI) circuits.
  • Data mining, where the objective is a simple description that summarizes the content of some data.

software

The MVSIS logic network is an extension of the traditional boolean network to include multi-valued nodes, each with its own range. MVSIS includes all the technology-independent transformations of SIS for combinational logic synthesis generalized from binary to multi-valued case, e.g. algebraic decomposition and observability don't care based node minimization. The domain of these optimizations is expanded by opening up multi-valued possibilities. It also includes transformations specific to multi-valued nodes such as combining binary nodes and producing multi-valued ones and vice versa, node minimization by exploring non-determinism in the network, and bidecomposition into multi-valued MIN/MAX gates, etc.

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publications

  1. A Theory of Non-Deterministic Networks
    Alan Mishchenko and Robert Brayton
    International Workshop on Boolean Problems, 2002.
    (PDF, PPT)
  2. A Theory of Non-Deterministic Networks
    Alan Mishchenko and Robert Brayton
    Accepted to IEEE TCAD, 2005.
    (PDF)
  3. Simplification of Non-Deterministic Multi-Valued Networks
    Alan Mishchenko and Robert Brayton
    IEEE/ACM International Conference on CAD, ICCAD 02, Santa Clara, November 2002. also in the Notes of the International Workshop on Logic Synthesis, New Orleans, June 2002
    (PDF, PPT)
  4. Reducing Multi-Valued Algebraic Operations to Binary
    Jie-Hong Jiang, Alan Mishchenko and Robert Brayton
    Design Automation and Test in Europe, DATE 2003, to appear. also in the Notes of the International Workshop on Logic Synthesis, New Orleans, June 2002
    (PDF, PPT)
  5. A Boolean Paradigm in Multi-Valued Logic Synthesis
    Alan Mishchenko and Robert K. Brayton
    In the Notes of the International Workshop on Logic Synthesis, New Orleans, June 2002
    (PDF, PPT)
  6. Optimization of Multi-Valued Multi-Level Networks
    M. Gao, J-H. Jiang, Y. Jiang, Y. Li, A. Mishchenko, S. Sinha, T. Villa and R. Brayton
    In the Proceedings of the International Symposium on Multiple-Valued Logic, 2002
    (PS, PPT)
  7. MVSIS
    Minxi Gao, Jie-Hong Jiang, Yunjian Jiang, Yinghua Li, Subarna Sinha and Robert Brayton
    In the Notes of the International Workshop on Logic Synthesis, Tahoe City, June 2001
    (PS, PPT)
  8. An implicit method for multi-valued network encoding
    Jie-Hong Jiang, Yunjian Jiang and Robert K. Brayton,
    In the Notes of the International Workshop on Logic Synthesis, Tahoe City, June 2001
    (PS)
  9. Minimization of Multiple-Valued Functions in Post Algebra
    Elena Dubrova, Yunjian Jiang and Robert Brayton,
    In the Notes of the International Workshop on Logic Synthesis, Tahoe City, June 2001
    (PS)
  10. Don't Cares and Multi-Valued Logic Network Minimization
    Y. Jiang, and R. K. Brayton,
    IEEE/ACM International Conference on CAD, ICCAD 00, Santa Clara, November 2000.
    (PS, PDF)
  11. Semi-Algebraic Methods for Multi-Valued Logic
    M. Gao, R. K. Brayton,
    IEEE IWLS 2000, International Workshop on Logic Synthesis 2000, Dana Point, CA, Workshop Notes 73-80, May 31 - June 2, 2000.
    (PS, PDF)
  12. Multi-valued Logic Synthesis
    R. K. Brayton, and S. P. Khatri,
    International Conference on VLSI Design, Goa, India, Jan 1999.
    (PS, PDF)
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