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Multi-Valued Logic Synthesis

Boolean Technology Mapping

Berkeley Language and Automata Manipulation

Combinational Verification

Physically-Aware Synthesis

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motivation

With smaller process geometries and increasing chip complexity, the traditional separation of logic synthesis and physical design leads to many iterations for design closure. Our research explores techniques to generate and utilize physical information during logic synthesis to help reduce time to design closure.

placement-aware divisor-extraction

We have developed an incremental placement algorithm that can be used in a variety of placement-aware logic synthesis methods. Given a point placement of a network, using the algorithm it is easy to compute the optimum location for a newly introduced node that minimizes the total increase in half-perimeter wire-length of the placement. We have applied this algorithm to placement-aware common divisor extraction where the goal is to reduce the congestion during routing. Our experiments on industrial and academic test-cases show that this technique significantly reduces congestion.

We are currently trying to extend other logic synthesis operations such as technology mapping with physical-awareness.

publications

  1. S. Chatterjee and R. Brayton, "An Incremental Placement Algorithm and Its Application to Congestion-Aware Logic Synthesis," Proc. ICCAD, 2004 (PDF).
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