AdoreA technology-independent module generator for Switched-Capacitor (SC) filters Adore is a technology-independent module generator for Switched-Capacitor (SC) filters. The layouts it generates for SC circuits include ratioed capaci- tors, double-throw switches, and operational amplifiers (op- amps). The circuits it is able to implement must have the fol- lowing characteristics: Every op-amp either has one input and one output (single-ended), or has two input and two output (fully- differential) terminals. Every capacitor has two terminals, one corresponding to the capacitor's top-plate, and another corresponding to the capacitor's bottom-plate. Every switch has five terminals. There is a terminal for capacitor connections, two terminals for op-amp connections, and for each of these two terminals there is a corresponding terminal for controlling clock connection. Only one of the op-amp connections can be grounded. Every capacitor top-plate is either directly connected, or switched to an input of an amplifier. Every capacitor bottom- plate is either directly connected, or switched to an output of an amplifier or an input to the circuit. For every capacitor, both terminals are either directly connected or switched to the opamp terminals. For every single-ended (fully differential) op-amp there is (are) one (two) capacitor(s) connected to the opamp's input and output terminals. One of the implications of the above restrictions is there cannot be any series or parallel connection of capacitors. Adore uses a fixed floor plan, and employs several algorithms to generate compact layouts for SC filters with small amounts of interconnect parasitics. The floor-planning strategy and some of the algorithms were discussed in .
The distribution tape includes all the files necessary to compile Adore version 2.1. Adore is written in the portable C language. It has been compiled under the VAX/UNIX system. Several files are included in the distribution to aid the compi- lation. The file named is a UNIX shell script which may be invoked by typing the command: The invocation of this command will result in the generation of the object files and the linking of The executable file is created. Adore can then be executed by issuing the command Adore circuitName [technologyName], where is a command line argument specifying the name of the circuit for which Adore is to generate the layout, and is a command line argument specifying the technology to be used by the program.
The termworking directory will refer to the directory of the file system to which the user is currently attached. Adore requires the presence of two input files in the working directory. The exe- cutable file need not reside in the working directory, however Adore searches for the input files in the working directory. The 2 input files which must be prepared by the user are: circuit- Name, and technologyName . The prefix to the input files ( cir- cuitName ) is the name of the circuit as entered on the command line when issuing the command: The file circuitName contains information regarding connectivity of circuit elements, capacitor values, and library names for op-amps and switches. The input format of Adore is similar to that of SPICE. Each element in the circuit is specified by an element card that contains the element name, the circuit nodes to which the element is connected, and parameter value(s) or library name of the circuit element. Nodes are name or number fields, and the datum (ground) node must be numbered zero (0). The first letter of the element name speci- fies the element type. A card has the following general form: Where is a name field starting with letter C, and are the plate connections of the capacitor, and is the size of capacitor in Farads. An card has the following general form: where is a name field starting with letter E, and are the positive and negative output nodes, respectively, and and are the positive and negative input nodes, respectively. The is pointer to op-amp's library location in the file system. A card has the following general form: where is a name field starting with letter S, is a switch node for connection to capacitor plates, and are switch nodes for connection to op-amps, and and are switch nodes for connections to controlling clocks for Namp_1 and Namp_2 nodes, respectively.
If no is specified for the switch, the layout for the switch is generated from technology information provided in a separate file. A card has the following general form: where is a name field starting with letter V, and and are the positive and nega- tive nodes, respectively. A card has the following general form: where is a name field starting with letter O, and and are the positive and negative nodes, respectively. The file technolo- gyName contains all the technology dependent information such as spacing rules and minimum unit-capacitor side dimension. Each line entered in this file is as follows: The parameters that are defined in this file are: - name of p-well layer as it appears in the layout description file, - name of p-diffusion layer, - name of n-diffusion layer, - name of metal layer, - name of bottom poly-silicon layer ( bottom plate of capacitors ), - name of electrode layer ( top plate of capacitors ), - name of select layer, - name of contact between metal and bottom poly-silicon layers, - name of layer used for extracting geometry information from op-amp and switch layout modules, - minimum resolution of mask generator, - type of topplate connection, 1 if contact to top-plate is allowed, 2 otherwise - minimum allowable unit capa- citor side dimension, - capacitance per unit-area in Farads/micron**2, - "yes" if shielding is allowed, - metal width for interconnects, - poly-silicon width for interconnects, - con- tact dimension for a square contact, - extension of capacitor bottom plate beyond its top plate, - spacing between adjacent poly-silicon lines, - spacing between adjacent metal lines, - separation of two adjacent contacts, - metal overlap of contact, - poly overlap of contact, - spacing between poly-silicon and contact, - separation of capacitor top plate and contact, - minimum separation of opamp blocks in x direction, - n-diffusion overlap of contact, - spacing of n-diffusion and contact, - p- diffusion overlap of contact, - spacing of p-diffusion and con- tact, - poly extension beyond the active n-diffusion, - poly extension beyond the active p-diffusion, - poly to n-diffusion spacing, - poly to p-diffusion spacing, - separation of metal line and active n-channel area, - separation of metal line and active p-channel area, - p-well overlap of n-diffusion, - p-well overlap of p-diffusion, - p-well and p-diffusion spacing, - spac- ing between p-wells, - select overlap of p-diffusion, - spacing of select layer and n-diffusion , - select overlap of channel, - minimum width of bus lines, - minimum length of n-channel transistor, - minimum length of p-channel transistor, - minimum width of n-channel transistor, - minimum width of p-channel transistor.
All the error messages are directed to the file The final layout is stored in the Oct  database. The layout can be checked by invoking VEM  and opening the view of Every op-amp, switch, and capacitor is labeled according to its circuit element name as it appears in The label for each overall input or output of the circuit is the circuit element name plus a '+' or '-' suffix depending on whether it is the positive or negative terminal of that circuit element. For example the labels for the element card
are for the input terminal for net and input terminal for net All the busses running through previously designed modules, are labeled according to their names as appear in those modules. For all the other busses created within the layout the following con- vention is used:
- the name for the ground busses - the name for the negative supply busses - the name for the positive supply busses. The programs and which are included in the tape, make it possible to convert Oct to CIF and vise versa.
Adore requires the following geometry information about every layout module it uses: The dimensions of the module in the x and y directions, The name and location of each terminal on the module, The name and location of each horizontal bus running through the module. This information should be appended to each module in the library by running
where contains the following information in the given order, to be appended to the module:
location of the module in the file system,
the leftmost x-coordinate of the module's bounding box,
the lowermost y-coordinate of the module's bounding box,
the rightmost x-coordinate of the module's bounding box,
the uppermost y-coordinate of the bounding box,
number of terminals,
for each terminal:
the leftmost x-coordinate,
the lowermost y-coordinate,
the rightmost x-coordinate,
the uppermost y-coordinate,
number of horizontal busses through the module,
for each bus:
the lowermost y-coordinate,
the uppermost y-coordinate.
If the module is an op-amp the following names should be used for its terminals:
INPUT_MINUS - the inverting input,
INPUT_PLUS - the non-inverting input,
OUTPUT_MINUS - the negative output,
OUTPUT_PLUS - the positive output.
If the module is a double-throw switch, then the following names should be used for its terminals:
AMP1TERM, CAPTERM, AMP2TERM,
CLK1TERM, CLK1BART, CLK2TERM, CLK2BART.
CAPTERM is periodically switched between AMP1TERM and AMP2TERM,
CLK1TERM is the terminal for the clock controlling the con- nection to AMP1TERM,
CLK1BART is for connection to the complement of this clock (could be missing),
CLK2TERM is the terminal for the clock controlling the con- nection to AMP2TERM,
and CLK2BART is for connection to the complement of this clock (could be missing).
Adore is an experimental program that is not yet complete. Many of its features are unfinished and unpolished. The follow- ing paragraphs describe some of the limitations. The layouts generated for fully differential circuits do not have symmetrical routing. If the program is to be used for fully differential applications, manual routing changes will be necessary. The user is responsible for correct input format. Incorrect input might result in a core dump. The generated layouts should be checked for design rule violations, even though such violations are very unlikely. Currently the program supports only technologies where contact to the top plate of the capacitor is permitted.
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