Digital Circuit Design for Minimum Transient Energy

Vishwani Agrawal

Abstract

We provide a theoretical basis for reducing or completely eliminating the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized when every gate has no more than one output transition per clock cycle. This condition is achieved for a gate when the gate delay equals or exceeds the maximum difference between path delays at gate inputs. In practice, path delays are adjusted either by increasing gate delays or by inserting delay buffers. The minimum transient energy design is obtained when no delay buffer is added. This design requires possible increases in gate delays to meet the minimum energy condition at all gates. However, the delay of the critical path may be increased. In an alternative design, where the critical path delay is not allowed to increase, delay buffers may have to be added. A linear program makes trade-offs between minimum transient energy and critical path delay. In an extreme design where the delay of the circuit increases three times, an optimized four-bit ALU circuit consumes 53% peak and 73% average power in comparison to the unoptimized circuit, as determined by Spice simulation. This work was done in collaboration with M. L. Bushnell of Rutgers University, G. Parthasarathy (UC, Santa Barbara) and R. Ramadoss (Lucent).


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