Electronic Systems Design Seminar
http://embedded.eecs.berkeley.edu/esd-seminar

mugshot


Low-Latency Interfaces for Mixed-Timing Domains

Prof Steven Nowick
Columbia University

Wednesday, Nov 28, 2001, 1:00pm-2:00pm
540AB Cory Hall (DOP Center Classroom)

Abstract

A critical challenge in designing Systems-on-Chip is to handle multiple timing domains. In this talk, we introduce a complete set of interface components which mediate between subsystems operating at different rates: (a) mixed-clock (sync-sync), (b) async-sync, and (c) sync-async.

The components have low-latency, and can be made arbitrarily robust with regard to metastability and interface operating speeds. The mixed-clock inteface, in particular, has advantages over recently-patented components from Intel.

The interface components are then modified to work between systems with very long interconnection delays, by migrating a single-clock solution by Carloni et al. (for "latency-insensitive" protocols) to mixed-timing domains.

The talk will also include a short overview of some of the speaker's other recent research: on high-speed asynchronous pipelines, and on CAD tools for asynchronous systems.

Speaker

Steven M. Nowick is an Associate Professor of Computer Science at Columbia University. He received a Ph.D. in Computer Science from Stanford University in 1993, and a B.A. from Yale University. His Ph.D. dissertation introduced an automated synthesis method for locally-clocked asynchronous state machines, and he formalized the asynchronous specification style called "burst mode". His research interests include asynchronous circuits, VLSI CAD, low-power and high-performance digital systems, and formal verification of finite-state concurrent systems.

In 2000, he received two large-scale NSF ITR awards, one to develop CAD tools for the synthesis of asynchronous systems, and the other for asynchronous low-power 3rd-generation wireless design. He received an NSF Faculty Early Career (CAREER) Award (1995), an Alfred P. Sloan Research Fellowship (1995) and an NSF Research Initiation Award (RIA) (1993). He received Best Paper Awards at the IEEE Async-2000 Symposium and 1991 IEEE International Conference on Computer Design, and was Best Paper Finalist at at the IEEE Async-98 Symposium and the 1993 Hawaii International Conference on System Sciences.

Prof. Nowick was co-founder/program co-chair of the 1st IEEE "Async" Symposium (1994), was program co-chair of the 5th IEEE "Async" Symposium (1999), and is program chair of the 11th IEEE/ACM International Workshop on Logic & Synthesis (IWLS-2002). He has been a member of over 25 international program committees, including ICCAD, DATE, ICCD, Async, TAU, VLSI Design and ARVLSI. He was also a Guest Editor of a special issue of the journal, "Proceedings of the IEEE" (v. 87:2, Feb. 1999), on asynchronous circuits and systems, and is co-author (with Robert Fuhrer) of the Kluwer book "Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools" (2001).

 

You are not logged in 
Contact 
©2002-2017 U.C. Regents