Electronic Systems Design Seminar
http://www-cad.eecs.berkeley.edu/esd-seminar

Abstract

Functional verification is generally accepted as the most time consuming part of the design cycle, taking up to 70% of the investment before tape-out. At the same time functional failures are the leading cause for Silicon re-spins. A host of verification techniques are used to counter these trends. Prominant among these is dynamic, or simulation based, functional verification.

Dynamic functional verification evolved from an intuitive and manual process into a highly automated methodology, driven by constraint based test generation and the underlaying constraint resolution algorithms. Functional coverage, defined over the architecture state space, guides the verification process. This is a predictable methodology that scales well compared to methods that operate directly on the design state space.

Speaker

Morley Matthew obtained a masters degree in computer science and completed a PhD in formal methods at the University of Edinburgh in 1992. For his postdoctoral research Matthew spent three years in Bonn in Germany working on languages for embedded software design, and a couple of years at the University of Leeds in England working on asynchronous hardware design with Prof. Graham Birtwistle. Matthew joined Verisity at their R&D headquarters in Israel in 98 to work on the formal semantics of their e language. Matthew now works for Verisity in Mountain View, CA. where he is project leader for eCelerator, their new testbench synthesis product.