VLSI Interconnect Layout Optimization In Deep Submicron Designs

Abstract

In the first part of my talk, I shall present the theory and general technique of the local refinement (LR) based optimization, which was developed from our research on interconnect layout optimization. It has been succefully applied to optimal wire sizing, simultaneous device and wire sizing under the general table-lookup based device delay models, and global interconnect sizing and spacing under the general coupling capacitance models. We believe that the LR-based optimization will find applications in many other layout and synthesis optimization problems.

In the second part of my talk, I shall discuss the trend of interconnect performance as implied by the newly revised National Technology Roadmap for Semiconductors (NTRS'97, draft), and show the impact of various interconnect optimization techniques on interconnect performance in each technology generation (from the 0.25um to 0.07um technology generations).

Web Site: http://cadlab.cs.ucla.edu/~cong