Code Scheduling for Media Hardware Platforms

Abstract

Media processors exhibit two salient features that make them look different from standard microprocessors:

- they usually process a multitude of well characterized data streams representing a variety of information types such as MPEG-video, -audio, Teletext and general data;

- as they are as a rule imbedded (for instance in a set-top box) they have to operate under strict real time cycle budgets to maintain a continuous and undisturbed service to the user.

The architectures involve a number of domain specific processing units embedded into a carefully designed memory structure and connected by highly flexible interconnect. The real time cycle budgets require a diligent code generation by the respective compilers. The talk presents some concepts for instruction and/or code scheduling applied at compile time addressing the instruction level parallelism. Next to the handling of basic blocks also conditionals, code-motion/speculative execution and loop-folding are discussed.

Some (real life) examples are given. Those examples show that the new methods offer improved control over the system performance. In certain instances cycle budgets have been met that were not satisfiable with earlier methods. The methods also bear significance for VLIW architectures.