THE BEGINNING OF THE END FOR STUCK-AT-FAULT BASED TESTING
Historically, test patterns for digital circuits have been produced by
targeting a specific fault model such as the set of all single stuck-at
faults, the set of all bridging faults, or some set of delay faults.
All of the major CAD companies have tools for test pattern
generation, and they do fault simulation based upon such models. In this
presentation, we will demonstrate that the quality of tests produced
using such models declines rapidly as the fault coverage approaches 100%.
An alternate test generation method is proposed where the objective
is to maximize defect detection by probabilistic "defect excitation" and
deterministic "defect-induced error observation."
Results obtained by using this approach
will be presented for a subset of the ISCAS benchmark circuits, and
the superiority of this approach over existing industry practice will