DETERMINING THE PERFORMANCE, COST AND CORRECTNESS OF PROCESSOR-BASED SYSTEMS

Abstract

In this talk I will present a technique for estimating processor performance and cost and a technique for verifying the correctness of processor pipelines. The estimation technique is based on an algorithm for partitioning RTL Verilog models into datapath and control blocks. Experiments demonstrate the efficacy of this algorithm in improving area estimates and generating simple floorplans. The pipeline verification technique is based on a scalable, formal methodology for analyzing pipelines called unpipelining. The key advantages of unpipelining are that it specifically targets pipeline control, making it more efficient; it requires no explicit specification, since it compares hardware against itself; it can be used within the broader framework of hierarchical verification; and, it can be easily extended to handle certain complex pipelined structures. For more information on these projects see the website below

Web Site: http://getafix.stanford.edu/cad