DYNAMIC LOGIC SYNTHESIS


Abstract

I will describe our research plan to develop automatic logic synthesis (and layout) capabilities for random logic blocks in which the majority of the logic is implemented with dynamic CMOS gates. We are currently developing the four dynamic logic synthesis and layout tools listed below. Although each of the synthesis tools will be aimed primarily at random (control) logic synthesis, the methods could be used for datapath as well.

  • Clock-delayed (CD) domino This is a new single-rail dynamic logic family. We are currently developing a new technology mapping algorithm that will utilize more complex gates than in our current approach. No pull-down path greater than 2 transistors will be permitted. Tremendous speed ups over static logic have been obtained (2.2 to more than 6 times faster) since considerably fewer logic levels are needed and each gate is really fast since it's limited to pull-down chains of no more than 2. Sun Microsystems is currently using our CD domino synthesis tool.

  • Mixed dynamic-static logic In this approach, the random logic description is first minimized and made positive unate (just as if it were dual-rail domino). We then apply a new technology mapping algorithm (which turns out to be optimal) that ensures that each dynamic gate (or cell) will have no pull-down path greater than 2 transistors and that each static gate (cell) will have no pull-up path greater than 2 transistors. Then we must make the network "two colorable" (i.e. a dynamic gate can only drive a static and vice versa). The algorithms for these steps are quite interesting. This will be at least as fast as dual-rail domino, but will use considerably less area and power. Conventional domino logic clocking is employed.

  • Decomposition into two-level logic structures We are developing a novel tool which takes a minimized random logic description and automatically decomposes into multiple area-efficient two-gate-level logic structures. Each two-level structure is extremely fast and compact since it is implemented as a CD domino NOR-OR structure. Not only is it two gate levels, but each "level" has a pull down path of one logic transistor for maximum speed. We have observed tremendous speed ups over static CMOS for the MCNC benchmark set.

  • Self-resetting dynamic logic In this synthesis tool, the random logic is first minimized (using Synopsys or SIS) and then is passed on to our novel technology mapping algorithm which results in a decomposition into gates having a longest pull down path of two logic transistors. The resulting netlist is then levelized. Utilizing a variant of the CD domino technique, each level (or stage) is made self-resetting. A stage goes into precharge as soon as it has finished evaluating AND the succeeding stage has finished evaluating. Also, a stage enters evaluation as soon as it has finished precharging AND the previous stage has finished evaluating. This tool is particularly promising for pipeling applications. The latency is two stage delays (keep in mind that each stage delay is quite short, since each gate has a maximum pull-down chain of 2 devices). Note that this approach to pipelining requires no explicit latches and no signals must be propagated through latches. The self-resetting tool can also be used to synthesize very fast non-pipelined circuits, in fact, much faster than static CMOS.


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